Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating
Reexamination Certificate
2000-09-26
2003-03-25
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
By integrating
C327S344000, C327S554000, C327S095000
Reexamination Certificate
active
06538491
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods and circuits for compensating the effect of switch resistance on settling time of high speed switched capacitor circuits.
2. Description of the Background Art
With the advent of MOS sub-micron technology circuits that function at low supply voltages, analog circuits must be implemented with minimal voltage headroom. An important class of analog circuits is based on the switched capacitor principle. These circuits include sample and hold circuits, track and hold circuits, switched capacitor amplifiers, switched capacitor filters, analog to digital converters (ADCs), chopper based circuits, and the like, and are used in most analog front-end solutions for mixed signal integrated circuits. In CMOS technology, such circuits are usually based on an interconnection of operational transconductance amplifiers (OTA) and capacitors by means of switches. Examples of conventional switched capacitor circuits can be found in
Proceedings of the IEEE
, “Switched-Capacitor Circuit Design” by Gregorian et al. (vol. 71, no. 8, pp 941-966, August 1983) and
Design of Analog Integrated Circuits
by Laker et al. (McGraw Hill, 1994, p 810). The need to design these switched capacitor circuits and use all available speed from a certain technology leads to both OTA and switch optimization within the limited voltage budget.
One of the figures of merit for these discrete-time analog processing circuits is the output settling time within a predefined error. The value of the output settling time dictates or limits some of the most important performance figures of these circuits, such as sampling frequency, harmonic distortion, signal to noise and distortion ratio, effective number of bits, signal processing bandwidth, etc.
The on-resistance of the switches connected in series with the switched capacitors create parasitic poles that adversely impact the settling performance of these circuits. The low supply voltage (low gate overdrive voltage) leads to higher switch on-resistance and degrades settling performance. In order to reduce the on-resistance, larger width transistors can be used. However, such larger width transistors increase both parasitic capacitance and clock feed-through, thus degrading settling performance. There is therefore a need to compensate the adverse effect of switch resistance on settling time.
A conventional approach to the problem of reducing the adverse effects of switch resistance on settling time includes using NMOS transistor based switches that connect plates of the switched capacitors to lower voltage nodes, so that the voltage gate overdrive is large enough and constant. All remaining switches of the circuit are CMOS transistor based switches. The sizes of the various transistors are determined assuming that the bandwidth of the switches and the capacitors together is much higher than the bandwidth of the OTAs and the capacitors. When voltage and speed are not limiting factors, the sizes of the MOS transistors are kept to a minimum and are usually constant throughout the design.
For example,
FIG. 1
illustrates a conventional switched-capacitor circuit including OTA
400
and NMOS transistors that couple plates of the circuit capacitors to lower voltage nodes, or the ground potential in this instance. The circuit includes capacitor
411
having a first plate that is coupled to the inverting input of OTA
400
and that is also coupled to a first end of NMOS transistor
403
. Capacitor
411
also has a second plate that is coupled to a first end of NMOS transistor
401
, wherein second ends of NMOS transistors
401
and
403
are coupled to system ground. The second end of NMOS transistor
403
is also coupled to the non-inverted input of OTA
400
. The second plate of capacitor
411
is also coupled to a first end of CMOS switch
423
, which is illustrated in greater detail in FIG.
1
A. The second end of CMOS switch
423
is coupled to a previous stage of the switch-capacitor circuit that is not illustrated.
The conventional switched-capacitor circuit of
FIG. 1
further includes CMOS switch
425
having a first end that is coupled to the output of OTA
400
and a second end that is coupled to a first plate of capacitor
413
. NMOS switch
405
has a first end that is coupled to the first plate of capacitor
413
and a second end that is coupled to system ground. A second plate of capacitor
413
is coupled to the inverting input of OTA
400
, to complete a feedback path.
As further illustrated in
FIG. 1
, the next stage of the switched-capacitor circuit includes CMOS switch
427
having a first end that is coupled to the output of OTA
400
and having a second end that is coupled to a first plate of capacitor
415
. NMOS switch
407
includes a first end that is coupled to a second plate of capacitor
415
and includes a second end that is coupled to system ground. The gates of NMOS transistors
401
,
403
,
405
and
407
and the gates of CMOS switches
423
,
425
and
427
are typically driven by a control circuit that is not illustrated in
FIG. 1. A
primary disadvantage of a switched-capacitor circuit of this type is that the circuit is not appropriate for high speed operation due to large parasitic capacitance that is added to the circuit nodes by the CMOS switches.
If the relatively slower speed of the conventional circuit as described with respect to
FIG. 1
can not be tolerated, the extra capacitance added by the slow and large PMOS transistors of CMOS switches
423
,
425
and
427
and the extra capacitance added by the interconnect capacitance of the CMOS switches, must be reduced. Thus, a second conventional approach comprises eliminating the PMOS transistors of CMOS switches
423
,
425
, and
427
of the
FIG. 1
circuit. The CMOS switches are respectively replaced with NMOS transistors
417
,
419
and
421
as illustrated in
FIG. 2
, such that the circuit includes only NMOS transistor switches. Specifically, the circuit of
FIG. 2
is configured the same as the circuit of
FIG. 1
, except for NMOS transistor
417
that includes a first end that is coupled to the second plate of capacitor
411
and a second end that is coupled to the previous stage, NMOS transistor
419
that includes a first end that is coupled to the output of OTA
400
and a second end that is coupled to the first plate of capacitor
413
, and NMOS transistor
421
that includes a first end that is coupled to the output of OTA
400
and a second end that is coupled to the first plate of capacitor
415
.
The approach of the
FIG. 2
circuit has the advantage that only fast NMOS transistors are used for switches. However, a primary disadvantage of this approach is that the dynamic range of the circuit is reduced. Moreover, the sizes of the MOS transistors are determined by keeping the switch bandwidth much higher than the OTA bandwidth. As a result, the sizes of the switches must necessarily be large, so that even at high input or output voltages (low switch gate overdrive voltage), the switch bandwidth is much higher than the OTA bandwidth. This approach leads to a much tighter compromise between the dynamic range at the output of the circuit and the settling time at the output of the circuit.
To overcome the above-noted problems of the conventional all-NMOS switch circuit as illustrated in
FIG. 2
, the gate overdrive voltage for the switch transistors can be increased by means of an on-chip voltage multiplier. There are two conventional alternatives to this approach. In a first alternative as illustrated in
FIG. 3
, voltage multiplier
431
and level shifters
433
are implemented to ensure that the switch control voltage of the NMOS switches are constant and higher than the supply voltage Vdd. The circuit of
FIG. 3
is configured the same as the circuit of
FIG. 2
, except for level shifters
433
that drive the gates of NMOS transistors
401
,
403
,
405
,
417
and
419
, and except for voltage multiplier
431
which multiples supply voltage Vdd and provides the higher multiplied
Callahan Timothy P.
Nguyen Hai L.
Oki America Inc.
Volentine & Francos, PLLC
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