Method and circuitry for testing a programmable logic device

Details Method and circuitry for testing a programmable logic device Method and circuitry for testing a programmable logic device

1989-12-04

1991-06-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307469, 371 222, H03K 19177

Patent

active

050234854

ABSTRACT:
A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programmning the device's logic array (22).

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patent: 4740919 (1988-04-01), Elmer
patent: 4780628 (1988-10-01), Illman
patent: 4857773 (1989-08-01), Takata et al.
patent: 4879688 (1989-11-01), Turner et al.
"Fault Detection in PLAs", Righbati, Simon Fraser University, IEEE Design & Test, Dec. 1986, pp. 43-49.
"Implementing a Built-In Self-Test PLA Design", Treuer et al., McGill University, IEEE Design & Test, Apr., 1985, pp. 37-48.
Cypress Semiconductor AAL C22V10 Specification Sheet.

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