Method and circuitry for supplying clock to internal circuit

Details Method and circuitry for supplying clock to internal circuit Method and circuitry for supplying clock to internal circuit

2001-01-25

2002-03-12

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S116000

Reexamination Certificate

active

06356128

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and circuitry for supplying a system clock signal to an integrated circuit (or internal circuit) of a semiconductor device, such as a microcomputer, including a built-in phase-locked loop (i.e., PLL) frequency multiplier.
2. Description of the Prior Art
Referring now to
FIG. 9
, there is illustrated a schematic circuit diagram showing the structure of prior art clock supply circuitry including a PLL frequency multiplier, the clock supply circuitry being built in a semiconductor device. In the figure, reference numeral
10
denotes the semiconductor device including the prior art clock supply circuitry, numeral
20
denotes the PLL frequency multiplier for generating a frequency-multiplied clock signal from an input clock signal, the frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of the input clock signal, numeral
30
denotes an oscillator driving circuit for driving an external oscillator connected between an input terminal Xin and an output terminal Xout, numeral
40
denotes a PLL output supply circuit for delivering the frequency-multiplied clock signal from the PLL frequency multiplier
20
as a system clock signal to an integrated circuit
50
after counting a pulse of the input clock signal applied to the PLL frequency multiplier
20
a predetermined number of times, when returning the clock supply circuitry from a stop state in which it is stopping the supply of the system clock to the integrated circuit
50
to its original state or clock supply state in which it is supplying the system clock signal to the integrated circuit
50
, numeral
401
denotes a counter for reloading a maximum count value thereinto and resetting its output so as. to put its output at a “Low” level every time a control signal or stop instruction signal applied thereto becomes a “High” level, and for starting counting down pulses of the input clock signal applied to the PLL frequency multiplier
20
and for furnishing an output at a “High” level when it underflows, numeral
402
denotes an SR flip-flop having an S terminal connected to an output terminal of the counter
401
and an R terminal for receiving the stop instruction signal, numeral
403
denotes a switch having a control terminal connected to a Q terminal of the SR flip-flop
402
, numeral
60
denotes an SR flip-flop having an S terminal for receiving a recovery instruction signal and an R terminal for receiving the stop instruction signal, and numeral
70
denotes a switch having a control terminal connected to a Q terminal of the SR flip-flop
60
. The system clock signal that is the output (or PLL output) of the PLL frequency multiplier
20
can be applied, by way of the switch
403
, to the integrated circuit
50
.
In operation, the counter
401
reloads the maximum count value thereinto and resets its output so as to put its output at a “Low” level every time the stop instruction signal applied to a control terminal thereof becomes a “High” level. When the Q output of the SR flip-flop
402
becomes a “High” level, the switch
403
is brought into conduction or placed to the ON position. In contrast, when the Q output of the SR flip-flop
402
becomes a “Low” level, the switch
403
is brought out of conduction or placed to the OFF position. Similarly, when the Q output of the SR flip-flop
60
becomes a “High” level, the switch
70
is brought into conduction or placed to the ON position. In contrast, when the Q output of the SR flip-flop
60
becomes a “Low” level, the switch
70
is brought out of conduction or placed to the OFF position. A signal passing through each of the two switches
403
and
70
has either a “High” level or a “Low” level according to whether a corresponding input signal has a voltage greater than or equal to or less than a threshold value.
A clock generating device
11
as shown in
FIG. 10
can be connected to the input terminal Xin of FIG.
9
. As an alternative, an external oscillator
12
as shown in
FIG. 11
can be connected between the input terminal Xin and the output terminal Xout.
First, a description will be made as to the operation of the clock supply circuitry when a clock generating device
11
is connected to the input terminal Xin, as shown in FIG.
10
. While the clock supply circuitry is placed in a clock supply stopping state, i.e., stop state in which it is stopping the supply of the system clock signal to the integrated circuit
50
, both the PLL frequency multiplier
20
and the oscillator driving circuit
30
are at a stand still. When the clock supply circuitry is brought to the stop state, the stop instruction signal becomes a “High” level and the recovery instruction signal becomes a “Low” level. As a result, the SR flip-flop
60
is reset and its Q output becomes a “Low” level, and therefore the switch
70
is brought out of condition. When the stop instruction signal becomes a “High” level, the counter
401
reloads the maximum count value thereinto and resets its output so as to put its output at a “Low” level, and then starts counting down pulses of the input clock signal applied to the PLL frequency multiplier
20
. In this case, since no clock pulse is applied to the counter
401
, the counter
401
keeps its count value at the maximum count value. Furthermore, the SR flip-flop
402
is also reset and its Q output becomes a “Low” level, and therefore the switch
403
is brought out of condition. As a result, the output terminal of the PLL frequency multiplier
20
is disconnected from the integrated circuit
50
.
When the recovery instruction signal becomes a “High” level while the clock supply circuitry is placed in the stop state, the semiconductor device
10
starts a recovery process of canceling the stopping of the supply of the system clock signal to the integrated circuit. First, the PLL frequency multiplier
20
and the oscillator driving circuit
30
start working. Since the stop instruction signal simultaneously becomes a “Low” level, the SR flip-flop
60
is set and its Q output becomes a “High” level, and therefore the switch
70
is brought into condition. Although the PLL frequency multiplier
20
receives a stable clock signal from the clock generating device
11
, as shown in
FIG. 12
, the PLL output supply circuit
40
cannot supply the PLL output to the integrated circuit
50
immediately after it receives the frequency-multiplied clock signal because some interval of time is required for the frequency-multiplied clock signal (or PLL output) from the PLL frequency multiplier
20
to become stable. In order to keep the switch
403
being in the OFF position until the PLL output becomes stable, the counter
401
of the PLL output supply circuit
40
counts down pulses of the input clock signal from the maximum count value. When the counter
401
underflows, it furnishes an output at a “High” level. As a result, the SR flip-flop
402
is set and the switch
403
is brought into conduction or placed to the ON position, and therefore the frequency-multiplied clock signal from the PLL frequency multiplier
20
is supplied as the system clock signal to the integrated circuit
50
. The recovery process is thus completed. The length of time that elapses until the counter
401
underflows after the recovery process is started and the input clock signal is then applied to the counter
401
corresponds to the maximum count value set to the counter
401
. The maximum count value is predetermined based on the simulated or measured longest time required for the PLL output to become stable so that the maximum count value allows for a margin. The longest time can be determined by estimating the time required for the output of the PLL frequency multiplier to become stable, and either performing circuit simulations in consideration of variations in ambient temperature and power supply voltage or performing experiments under a variety of operating conditions. As shown in
FIG. 12
, the PLL output supply circuit
40
brings t

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