Method and circuitry for minimizing clock-data skew in a bus sys

Details Method and circuitry for minimizing clock-data skew in a bus sys Method and circuitry for minimizing clock-data skew in a bus sys

1994-01-07

1995-07-11

Chin, Stephen

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

375371, 370103, 370108, H04L 700

Patent

active

054328233

ABSTRACT:
A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

REFERENCES:
patent: 4247817 (1981-01-01), Heller
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4519034 (1985-05-01), Smith et al.
patent: 4785394 (1988-11-01), Fischer
patent: 4811202 (1989-03-01), Schabowski
patent: 4860198 (1989-08-01), Takenaka
patent: 4949361 (1990-08-01), Jackson
patent: 4998262 (1991-03-01), Wiggers

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