Method and circuitry for equalizing the differing delays of semi

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307511, 307516, 307303, 324 99D, 324158R, 328 55, 328 56, H03K 5159

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042874378

ABSTRACT:
For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times.
The digital control circuit comprises a comparator circuit where the signal delay of a clock pulse is compared in a chain of inverters with the very precisely defined clock interval. Depending on the result of the comparison, the count of an up-down counter is incremented or decremented by one. The resulting count is decoded and converted into a corresponding voltage for operating the circuits of the semiconductor chip. Subsequently, the above described steps are repeated until the difference .DELTA.t between the arrival of a clock pulse delayed by the chain, and the following undelayed clock pulse approaches zero.

REFERENCES:
patent: 3271688 (1966-09-01), Gschwind et al.
patent: 3743850 (1973-07-01), Davis
patent: 3970919 (1976-07-01), Butcher
patent: 4017750 (1977-04-01), Voorman
patent: 4216544 (1980-08-01), Boleda et al.

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