Boots – shoes – and leggings
Patent
1989-04-07
1991-07-30
Shaw, Dale M.
Boots, shoes, and leggings
G06F 752
Patent
active
050364820
ABSTRACT:
A method nad circuitry for multiplication in a digital system is described. The circuitry includes a partial product generator, a carry-save adder, a sum latch, a carry latch, an adder, a latch, circuitry for truncating, and coupling circuitry. A method and circuitry for optimizing a speed of a subsequent multiplication in a digital system is described. Circuitry for optimizing multiplication clock cycles in a digital system is described.
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Intel Corporation
Shaw Dale M.
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