Method and circuitry for decreasing the recovery time of an MOS

Details Method and circuitry for decreasing the recovery time of an MOS Method and circuitry for decreasing the recovery time of an MOS

1991-07-26

1993-09-21

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307352, 307362, 307491, 307497, H03K 524, H03K 19017

Patent

active

052472108

ABSTRACT:
Method and circuitry for decreasing the recovery time of an MOS differential voltage comparator after an input voltage overdrive. At the beginning of a comparison cycle a reverse voltage is momentarily applied between the gates and sources of the input pair of source-coupled MOS transistors of sufficient magnitude to form a charge accumulation layer in the channel region of each of the transistors. Operating the differential voltage comparator in such manner substantially decreases the time required for the transistors to recover from an imbalance in their electrical characteristics caused by the input voltage overdrive.

REFERENCES:
patent: 4150311 (1979-04-01), Matsuda et al.
patent: 4611130 (1986-09-01), Swanson

Affiliated with

Also associated with

Rating

Method and circuitry for decreasing the recovery time of an MOS does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuitry for decreasing the recovery time of an MOS , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuitry for decreasing the recovery time of an MOS will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1052705