Method and circuitry for correcting errors in recirculating memo

Details Method and circuitry for correcting errors in recirculating memo Method and circuitry for correcting errors in recirculating memo

1980-11-03

1982-12-21

Atkinson, Charles E.

Excavating

371 50, 371 71, G06F 1110, G11C 2900

Patent

active

043653324

ABSTRACT:
A method and circuitry are disclosed for correcting bit errors introduced by random events in a data recirculating memory, such as a charge coupled memory device or a bubble memory. The bit errors, caused by random events such as by alpha particle bombardment or other causes, are corrected in circuitry that generates row and column parity bits corresponding to various segments of the information stored in the memory. Changes in the row and column parity bits uniquely define the location of failed bits circulating through the memory even though each failed bit has no fixed address, so that error detection circuitry thereafter may correct the error during the next or a subsequent bit recirculating cycle. The invention facilitates the use of very large memories, for example, on the order of one billion bits or more.

REFERENCES:
patent: 3768071 (1973-10-01), Knauft et al.
patent: 3940601 (1976-02-01), Henry et al.
patent: 4037091 (1977-07-01), Beuscher
patent: 4175692 (1979-11-01), Watanabe
patent: 4216541 (1980-08-01), Clover et al.
patent: 4296494 (1981-10-01), Ishikawa et al.

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