Electricity: measuring and testing – Plural – automatically sequential tests
Reexamination Certificate
1999-11-16
2002-04-30
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Plural, automatically sequential tests
C324S076590, C324S076610, C714S726000, C714S729000
Reexamination Certificate
active
06380724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the testing of electronic circuits, and more specifically, to circuit level testing of integrated circuits.
2. Description of the Related Art
One important aspect that must be considered in the design of any integrated circuit is testability. In recent years, design for testability has become an even greater challenge due to the ever-increasing density of integrated circuits. Because of the high density of many integrated circuits, testing their internal logic solely by applying external stimuli has become impractical. An alternate method of testing the internal logic of an integrated circuit is to use scan chains.
A scan chain is created using the flip-flops (or latches or other clocked storage devices) of an integrated circuit. The output of a given flip-flop is coupled to the input of another flip-flop. A large number of flip-flops are connected in this manner, forming a scan chain that passes through the internal logic of an integrated circuit. The scan chain may be thought of as a serial shift register, in which values are shifted from one register flop to the next. Using this method, multiple scan chains may be formed in a given integrated circuit.
In order to test an integrated circuit using a scan chain, scan data (i.e. the test data, or test vector) is shifted into the chain, loading each element of the chain with a predetermined value. Following the initial loading, the circuit is then reverted to its normal operating mode, allowing the individual circuits to respond to the scan data. After allowing the circuits a sufficient time to respond, the scan data is shifted out of the scan chain, where it is compared with expected results to determine whether the chip is faulty.
One common type of flip-flop (or latch) circuit used in the formation of scan chains is the dual-ported flop. A dual-ported flop possesses both a data input and a scan data input, as well as a data output and a scan data output. In addition to the system clock input, a dual-ported flop also may include two scan clock inputs. One scan clock is used to load scan data into the flop, while the other is used to shift data out of the flop.
Despite the advantages provided by testing through scan chains, problems can arise when shifting scan data through the chain. One such problem arises when the state of a flop data output is disturbed during scan shifting. Scanning scan data through the flop can cause arbitrary changes in the state of the flop's data output. Such state changes can have undesired effects and may even cause damage to the circuit
FIG. 1
is a schematic of a one-hot multiplexer circuit (or passgate multiplexer circuit), and is used to illustrate a potential problem that can occur during scan shifting. The logic surrounding the one-hot multiplexer is designed so that only one of the three select inputs (S
0
, S
1
, or S
2
) is asserted at any given time. However, during scan shifting, a state change in a flop output may override the surrounding logic, causing two or more select inputs to be asserted at the same time. This can result in excess current being drawn from the output inverter. The excess current may damage or destroy the output inverter.
Problems such as the above example can force compromises in the design of an integrated circuit, compromise its testability, or both. For example, the problem illustrated above may be prevented by using traditional multiplexer circuits at the cost of using more circuit area to implement the same function. Alternatively, testing sequences can be designed to avoid these areas of the circuit, compromising its testability.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a method and circuitry for an undisturbed scannable state element. In one embodiment, the scannable state element includes a dual-ported level sensitive scan design (LSSD) style flop/latch circuit which is augmented with a shadow flop circuit. The dual-ported flop circuit includes both a master cell and a slave cell. A shadow flop circuit is coupled to the dual-ported flop circuit. The shadow flop circuit includes a master cell, and utilizes the slave cell of the dual-ported flop circuit. During scan operations, the scan data bypasses the master cell of the dual-ported flop, passing instead through the shadow flop circuit and the slave cell of the dual-ported flop. Scan data is then passed on to the next link in the scan chain through a scan data out (SDO) output coupled to the slave cell. Since, during scan, the scan data bypasses the master cell of the dual-ported flop (to which the data output of the flop is coupled), the state of the flop remains unchanged. Thus, the data output of the dual-ported flop is held steady, which may allow any circuit constraints to be met during the scan.
Control of scan operations, in one embodiment, is accomplished through the use of a shadow control logic circuit. The shadow control logic is configured to receive two clock inputs (scan clock one, or SC
1
, and scan clock two, or SC
2
), and a scan enable input. When the scan enable input is asserted, the two scan clock inputs may be used to latch scan data through the shadow flop, thus bypassing the master cell of the dual-ported flop. As a result, the state of the dual-ported flop may not be disturbed. If the scan enable input is not asserted, the two scan clock inputs may be used to load a predetermined state into the master cell of the dual-ported flop and shift data out of the flop for observation upon completion of the test. Each shadow control logic circuit can be used to control a plurality of shadow/dual-ported flop circuit combinations.
Thus, in various embodiments, the method and circuitry of a scannable state element allows scan operations to take place without disturbing the state of the dual-ported flop circuit During scan operations, scan data bypasses the master cell of the dual-ported latch circuit, passing through the shadow flop circuit instead. Since the state of the dual-ported flop circuit is not disturbed during the scan, the scannable state element may be able to meet the constraints of the circuitry under test, thus allowing greater testability without compromising circuit design. Since the shadow flop utilizes the slave cell of the dual-ported flop, shadow flop and shadow control circuitry may be implemented in designs containing dual-ported flops.
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IEEE Std. 1149.1 (JTAG) Testability Primer, Texas Instrument Inc. 1996.*
“Loading Test Patterns Into Complex Semiconductor Chips Using Isolated Outboard Level Sensitive Scan Design Chains,” IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, pp. 1202-1203.
Burd Robert C.
Correll Jeffrey A.
Mahurin Eric W.
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Merkel Lawrence J.
Metjahic Safet
Patel Paresh
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