Method and circuit to reduce jitter generation in a PLL...

Details Method and circuit to reduce jitter generation in a PLL... Method and circuit to reduce jitter generation in a PLL...

2002-04-25

2004-05-25

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C375S376000, C331SDIG002

Reexamination Certificate

active

06741108

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to reducing jitter in a phase locked loop (PLL), and more particularly to methods and apparatus for producing a reference frequency signal for a PLL using a reference frequency quadrupler.
A conventional phase locked loop (PLL) typically includes a frequency phase detector which receives a reference signal, a filter, a voltage-controlled oscillator (VCO), and a divider circuit. If the reference signal received by the frequency phase detector has a relatively low frequency, a large feedback divider ratio is required by the PLL. A large feedback divider ratio requires that the divider circuit have a relatively large number of dividers, which undesirably introduces phase “jitter” into the signals. The large feedback divider ratio also means that the loop gain of the PLL will be lower for a given supply voltage, which makes the gain distribution for noise less ideal and also increases jitter.
One solution to this problem is to increase the frequency of the reference signal received by the frequency phase detector. However, conventional XOR-based frequency doublers typically distort the duty cycle of reference signals due to integrated circuit (IC) process variations. This distortion may be severe enough to render the approach ineffective.
SUMMARY OF THE INVENTION
According to the present invention, a jitter reduction circuit for a phase locked loop (PLL) includes a first frequency doubler, a first equalizer having an input coupled to an output of the first frequency doubler, a second frequency doubler having an input coupled to an output of the first equalizer, a second equalizer having an input coupled to an output of the second frequency doubler, and a frequency phase detector having a first input coupled to an output of the second equalizer and a second input coupled to an output of a voltage controlled oscillator (VCO) of the PLL.
Each frequency doubler is configured to double a frequency of a reference signal provided thereto. The combination of the two frequency doublers in series quadruples the reference signal into the PLL. The first equalizer helps restore the duty cycle of the signal before it enters the second frequency doubler, and the second equalizer helps restore the duty cycle before the signal enters the PLL. The increased (quadrupled) reference frequency allows the PLL to have a smaller feedback divider ratio and therefore fewer dividers; fewer dividers result in less circuitry in the PLL feedback path which reduces jitter. A reduced divider ratio also allows a higher loop gain for a given supply voltage, which produces a more ideal gain distribution for noise and reduces jitter as well. Importantly as well, controls for the selection of the initial reference signal are advantageously provided.
The invention, embodied as a method, includes receiving a first reference signal, quadrupling a frequency of the first reference signal to produce a second reference signal, and equalizing the second reference signal to produce the PLL rat reference signal. The step of quadrupling a frequency of the first reference signal may include doubling a frequency of the first reference signal to produce an intermediate reference signal having a frequency that is twice that of the first reference signal. The step further may include doubling the frequency of the intermediate reference signal to produce a second reference signal having a frequency that is four times that of the first reference signal. The method further may include providing the second reference signal to the PLL.


REFERENCES:
patent: 5227671 (1993-07-01), Ehrlich
patent: 5241285 (1993-08-01), Jackson
patent: 5500627 (1996-03-01), Hulsing, II
patent: 5566204 (1996-10-01), Kardontchik et al.
patent: 5963071 (1999-10-01), Dowlatabadi
patent: 6107891 (2000-08-01), Coy
patent: 6198317 (2001-03-01), Chow et al.
patent: 6538520 (2003-03-01), Merrill et al.

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