Method and circuit of erasing a flash memory

Details Method and circuit of erasing a flash memory Method and circuit of erasing a flash memory

1999-09-27

2001-02-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185330, C365S185020

Reexamination Certificate

active

06195293

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit of erasing a flash memory cell which can minimize the occurrence of an instantaneous peak current occurring at the beginning of erasing operation of flash memory cell.
2. Description of the Prior Art
FIG. 1
shows a split gate type flash memory cell to illustrate a conventional method of erasing a flash memory cell.
To erase the flash memory cell, 0V is applied to a select gate electrode
4
of the flash memory cell, −12V is applied to a program gate electrode
5
, a source electrode
1
is floated, 0V is applied to a P-type substrate
3
and a source voltage Vcc is applied to a drain electrode
2
. At this time, electric charges accumulated in a floating gate electrode
6
are discharged to the drain electrode
2
by F-N tunneling so that the flash memory cell performs the erase operation.
FIGS. 2A and 2B
are waveform diagrams showing variances of voltages supplied to respective electrodes and of corresponding initial currents at the time of conventional erasing operation. Here, reference numeral E represents an erasing operation voltage, Q
1
represents a program bias voltage supplied to the program gate electrode, D represents a drain bias voltage supplied to the drain electrode and Q
2
represents a bias voltage for erasing. In
FIGS. 2A and 2B
, t
1
represents an entire erasing operation time, t
2
represents an initial erasing operation time, t
3
represents an erasing operation time, t
4
represents a read operation time, and t
5
represents an erasing confirmation operation time, and it can be noted that the instant peak current steeply rises at the initial erasing operation time t
2
.
In such a conventional erasing circuit, if a plurality of flash memory cells are simultaneously erased, a large current initially flows due to a tunneling phenomenon between the program gate electrode
5
and the drain electrode
2
so that a power of a device, that is, the instant peak current at the source voltage Vcc increased large. And there is a disadvantage that the power of a system using the flash memory device is accordingly influenced, which in turn influences other devices.
SUMMARY OF THE INVENTION
Therefore, the object of the invention is to provide a method and a circuit of erasing a flash memory cell which can removes the disadvantage by supplying, in step, the erasing voltage supplied to the drain electrode to reduce the voltage difference between the program gate electrode and drain electrode at the beginning of erasing operation of the flash memory cell.
To achieve the above object, a method of erasing a flash memory according to the present invention comprising, the steps of:
performing a first loop erasing operation so that a source electrode is floated, a program gate electrode is applied with a negative voltage and a drain electrode is supplied with an initial erasing voltage; and
performing a second loop erasing operation so that the source electrode is floated, the program gate electrode is applied with the negative voltage and the drain electrode is supplied with a normal erasing voltage higher than the initial erasing voltage.
A flash memory erasing circuit of the present invention includes:
a source voltage bias circuit for floating the source electrode;
a program gate voltage bias circuit for supplying a negative voltage to the program gate electrode;
a drain erasing voltage control circuit for generating a first and then a second voltage; and
a drain voltage bias circuit receiving the first and second voltages for first supplying an initial erasing voltage having a non-zero positive potential and then supplying a normal erasing voltage to the drain electrode.
The drain erasing voltage control circuit of the present invention includes:
an input circuit for receiving a first and a second control signal;
a logic circuit connected between a supply voltage Vcc and ground for generating the first and second voltages in accordance with at least one output of the input circuit and a charge pump; and
an output circuit connected between the supply voltage Vcc and an output terminal of the logic circuit, the output circuit being controlled by at least one output of the input circuit and the logic circuit.
The present invention can suppress with maximum the instantaneous peak current occurring at the time of erasing operation of the flash memory cell by weakly erasing at the beginning by using the weak erasing mode at the time of erasing operation of the flash memory cell and thereafter by reducing, in step, the voltage difference between the program gate electrode and drain electrode of the flash memory cell by proceeding the normal erasing mode.


REFERENCES:
patent: 5959893 (1999-03-01), Song
patent: 5978272 (1999-11-01), Fang et al.
patent: 6005809 (1999-12-01), Sung et al.

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