Method and circuit for trimming the internal timing conditions o

Details Method and circuit for trimming the internal timing conditions o Method and circuit for trimming the internal timing conditions o

1998-02-26

1999-12-28

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365233, 36523008, G11C 800

Patent

active

060090413

ABSTRACT:
A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.

REFERENCES:
patent: 5056064 (1991-10-01), Iwahashi et al.
patent: 5444666 (1995-08-01), Oh
patent: 5668949 (1999-03-01), Villa et al.
patent: 5883854 (1999-03-01), Becker
patent: 5889728 (1999-03-01), Rezcanu
patent: 5923610 (1999-07-01), Te

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