Method and circuit for triggering column select line for write o

Details Method and circuit for triggering column select line for write o Method and circuit for triggering column select line for write o

1998-11-18

2000-05-09

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518905, G11C 800

Patent

active

060612924

ABSTRACT:
Methods and circuits for triggering column select line for write operations in a multiple data rate (e.g., a double data rate) operation. A memory device includes a memory array that stores data values, an address logic circuit that generates an address for the memory array, and a column decoder. The column decoder couples to the address logic circuit and the memory array. The column decoder receives either a data strobe input signal (DQS) or a clock signal (CLK), or both, and activates a column select line for the memory array in response to one of the input signal(s).

REFERENCES:
patent: 5754481 (1998-05-01), Yabe et al.
patent: 5848014 (1998-12-01), Yukshing
patent: 5923613 (1999-07-01), Tien et al.

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