Method and circuit for timing the loading of nonvolatile-memory

Details Method and circuit for timing the loading of nonvolatile-memory Method and circuit for timing the loading of nonvolatile-memory

1995-02-21

1996-05-07

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365194, 365206, 365208, G11C 702

Patent

active

055153321

ABSTRACT:
A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.

REFERENCES:
patent: 4335525 (1982-06-01), Akatsuka
patent: 5056064 (1991-10-01), Iwahashi et al.
patent: 5057711 (1991-10-01), Lee et al.
patent: 5200926 (1993-04-01), Iwahashi et al.

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