Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-10-07
2001-10-09
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185090, C365S185200, C365S185030
Reexamination Certificate
active
06301157
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method and a circuit for testing memory cells in a multilevel memory device.
BACKGROUND OF THE INVENTION
It is known that one of the tests performed in the preliminary steps for checking a permanent memory device is a test which allows to identify the cells of memory devices that are not erased sufficiently by an exposure to ultraviolet rays or that lose their erased state for various reasons.
This test consists in comparing the threshold in all the cells of the memory matrix with the threshold of an appropriate reference cell by means of a normal read operation performed with a sense circuit constituted by a sense amplifier which receives in input a signal from a cell being tested and a signal from the reference cell.
In this case, the reference cell has a threshold which identifies it as neither programmed nor virgin.
The cells compared with the reference cell must therefore have a lower threshold in order to assuredly be virgin cells.
The memory cells rejected as a consequence of this check are made redundant by means of the redundancy lines, which therefore allow to restore the “damaged” cells and therefore preserve the integrity of the memory device.
In two-level memories, since the distance, in terms of difference in output signal, between the threshold of a virgin cell and the threshold of a programmed cell is rather large, it is not necessary to have, as in the previous case, a reference cell with a threshold that lies between the threshold of a virgin cell and the threshold of a programmed cell; the same effect is achieved by using a virgin cell as reference and by unbalancing the two branches of the sense amplifier.
In a multilevel memory, each individual cell must instead contain a plurality of logic states: for example, in a four-level memory there are four logic states, “11”, “10”, “01” and “00”, which are mutually separated by three reference levels (thresholds), designated respectively by Vr
1
, Vr
2
and Vr
3
in
FIG. 1
, which are used to discriminate the four logic states during reading.
FIG. 1
charts the threshold of a cell as a function of the number of cells.
The above-mentioned logic values that the cell can assume are mutually separated by the above-mentioned three references together with the supply voltage Vcc.
The condition in which the cell is erased in an optimum manner corresponds to the logic state “11”, in which the threshold of the cell is below the threshold of the lowest reference Vr
1
.
The curve plotted in the chart of
FIG. 1
shows the distribution of virgin cells.
For technological reasons, the choice of the references should not be made in advance, i.e., regardless of the device being considered, as instead occurs in a two-level memory.
Erasure of the matrix cells by means of ultraviolet rays in fact produces a statistical distribution of their thresholds (as shown in FIG.
1
), and since the above-described testing method eliminates memory cells whose threshold is higher than the reference Vr
1
, an excessively low threshold Vr
1
entails the risk of eliminating an excessive number of memory cells which are in the upper trailing part of the statistical distribution, so that the redundancy lines are not sufficient to replace all the eliminated memory cells.
Vice versa, an excessively high threshold Vr
1
reduces the interval between said threshold and the supply voltage Vcc, in which the upper references of Vr
2
and Vr
3
must be defined.
Therefore, since not only the thresholds of virgin cells but also the thresholds of cells written with a given logic value have a certain statistical distribution with respect to their average value, a reduction of the intervals above the minimum threshold Vr
1
that define the logic level entails an increase in the probability of an error when reading the cell.
The narrower the intervals between the logic write levels, the higher the likelihood that said logic levels will not be discriminated with sufficient precision.
SUMMARY OF THE INVENTION
The present invention provides a method and a circuit for testing memory cells, and, more particularly, for testing virgin memory cells in a multilevel memory that enables determination of an optimum lower reference threshold and replacement of any damaged cells with redundancy cells.
Within the scope of the present invention is a method for testing memory cells in a multilevel memory which provides for a measurement of the statistical distribution of the thresholds of the matrix cells from which the optimum lower threshold can be obtained.
The present invention also provides a method and a circuit for testing memory cells in a multilevel memory in which the intervals between the references above the minimum reference are wide enough to avoid memory cell read errors.
Another aspect of the present invention is to provide a method and a circuit for testing memory cells in a multilevel memory which can be implemented circuitally without any additional circuits with respect to those normally present in a memory device.
Yet another aspect of the present invention is to provide a method and a circuit for testing virgin memory cells in a multilevel memory which are highly reliable, relatively easy to provide and at competitive costs.
These and other benefits and advantages, which will become apparent hereinafter, are achieved by a method for testing virgin memory cells in a multilevel memory device having a plurality of memory cells, that includes:
reading the individual memory cells that constitute a memory device and comparing each one of said memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of said memory cells is lower than the threshold of said at least one reference memory cell or not;
determining the number of said memory cells whose threshold is higher than the threshold of said at least one reference cell;
said at least one reference memory cell being chosen with a gradually higher threshold; and
when said number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming said given reference threshold as lower reference threshold for said memory device, determining a statistical distribution of the thresholds of said memory cells.
REFERENCES:
patent: 5568419 (1996-10-01), Atsumi et al.
patent: 5602789 (1997-02-01), Endoh et al.
patent: 5694356 (1997-12-01), Wong et al.
patent: 5754558 (1998-05-01), Hayakawa et al.
patent: 0856850A2 (1998-08-01), None
Montanaro Massimo
Riva Marco
Rolandi Paolo
Galanthay Theodore E.
Hoang Huan
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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