Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se
Reexamination Certificate
2000-05-12
2003-07-01
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
C324S754090, C324S763010, C324S1540PB
Reexamination Certificate
active
06586921
ABSTRACT:
BACKGROUND OF THE INVENTION
When testing an integrated circuit (IC), the number of signals driven and received by the test equipment (tester) is typically equal to the number of signal pins of the IC. It is possible for an IC to have hundreds or thousands of signal pins, and the tester that tests these ICs can be very expensive because the cost of a tester is linearly dependent on the number of signals it drives and receives. It is desirable to minimize the number of signals that a tester must drive and receive from an IC, to reduce the cost of the tester or to permit more ICs to be tested in parallel by the tester.
When testing an IC at the wafer level (i.e., while it is still part of a wafer containing many of the ICs), a probe card which allows tester access to the individual ICs typically has the same number of probes as the number of bond pads on the IC. Bond pads are the metal sites to which a wire or solder will eventually be bonded to convey signal and power between an IC and a substrate or pins of an enclosing package. The quality of the probe to bond pad connection, the inductance of the probe card wires and probes, and the capacitances of these wires can all contribute to degraded signal integrity at high frequencies. For these reasons, as well as the material cost of each probe, it is desirable to minimize the number of probes needed for wafer-level testing of each IC.
Typical circuit elements that provide paths for leakage current to and from a circuit node, a pin (or bond pad) of an IC are shown in FIG.
1
. The leakage can be caused by many sources, including, but not limited to, electro-static discharge (ESD) protection diodes
19
,
20
, faulty metal-oxide-semiconductor (MOS) transistor gates
11
,
12
, pull-up circuits
15
,
17
, pull-down circuits
16
,
18
, and other semiconductor elements. Most ICs have specifications stating the maximum leakage current that the IC will have at any input pin or at any 3-state output pin when the output driver is disabled and the pin has high-impedance output. It is therefore important to test that these leakage currents are less than the specified maximum. The purpose of pull-up or pull-down circuits
15
-
18
is to “pull” the voltage of an un-driven pin to a higher or lower voltage such as V
DD
or V
SS
. Accordingly, for pins with pull-up or pull-down circuits
15
-
18
, it is usually important to test that the current is between a lower limit and an upper limit.
The standard terms used in industry for denoting input pin DC parameters are: IIL (maximum current for input at logic low), IIH (maximum current for input at logic high), VIL (maximum voltage for input at logic low), and VIH (minimum voltage for input at logic high). The standard terms for denoting output pin DC parameters are: IOL (maximum current for output pin at logic low), IOH (maximum current for output at logic high), VOL (maximum voltage for output at logic low while delivering IOL), and VOH (minimum voltage for output at logic high while delivering IOH).
Leakage current due to intrinsic current through reverse-biased diodes
19
,
20
and MOS transistor gates
11
,
12
is typically much less than 1 microamp (&mgr;A) in a fault-free circuit. Leakage current due to pull-up or pull-down circuitry
15
-
18
is typically between 10 and 150 &mgr;A. In some ICs, for example as shown in U.S. Pat. No. 5,670,890 issued to Colwell et al on Sep. 23, 1997, the pull-up and pull-down circuitry is disabled while testing the leakage current caused by other circuitry.
It is therefore important to be able to set different test limits for different pins. For example, pins with a pull-up circuit may require testing that the current is between −50 and −150 &mgr;A; pins with a pull-down circuit may require testing that the current is between +30 and 10 &mgr;A; other pins may require the current be between +1 and −1 &mgr;A.
Throughout this disclosure, the current at a pin is positive if it flows into the IC, and negative if it flows out of the IC, when the pin is connected to any voltage between V
DD
and V
SS
. Unsigned current may be positive or negative.
In general, the causes of leakage current are so diverse that the test limits are very tolerant of variation. Nevertheless, measuring currents at hundreds or thousands of pins of an IC can be expensive: the tester must have a parametric measurement unit (PMU) for each pin to allow testing all pins in parallel, or the tester must test one pin at a time if only one PMU is available.
It is typical in industry to specify the maximum leakage current as 1 &mgr;A even though the expected current is less than 1 nA, because the test time to verify 1 nA can be excessive. For example, the pin's capacitance to ground might be 1 picofarad (pF), but the tester coaxial cabling connected to the pin might have capacitance of 50 pF. The time for a 1 nA current to discharge 50 pF by 1 volt, is 50 ms, whereas if 1 &mgr;A is used, the discharge time is only 50 &mgr;s. Smaller voltage differences can be measured to decrease test time, but noise tolerance diminishes.
A standard technique for testing current at a pin is based upon connecting a current source to the pin, applying a pre-determined current (IIL or IIH, for inputs, and IOL or IOH, for outputs), and measuring the resulting voltage at the pin. This technique is used to measure a very wide range of currents, from amperes to nanoamperes, and can therefore measure output drive current and input leakage current. A standard variation of this technique is to continuously increase the current until a pre-determined pin voltage (VOL or VOH for outputs) is reached. Both techniques require direct connection to the pin under test.
Another prior art technique for testing leakage current at a pin is based upon connecting a voltage source to the pin via a high impedance resistor and measuring the resulting steady-state voltage across the resistor, for example as shown in U.S. Pat. No. 5,569,951 issued to Grace and DiPietro on Oct. 29,1996.
Prior art techniques exist for testing leakage current at a power supply pin of an IC, when all circuitry in the IC is inactive (or “quiescent”). This current is known as I
DDQ
and if it is excessive (e.g., greater than 100 &mgr;A), it may indicate that a fault exists somewhere among the thousands of MOS transistors of an IC, because when these transistors are inactive they normally conduct no current between the power and ground supplies. Some prior art I
DDQ
measuring techniques disconnect the IC from the power supply briefly (e.g., less than 1 ms), when the IC is known to be inactive, and connect the IC to the power supply via a resistance, for example, as shown in U.S. Pat. No. 5,371,457 issued to Lipp on Dec. 6, 1994. By measuring the voltage across the resistance, small currents are measured very quickly, before the voltage at the power supply pin of the IC decreases more than a few hundred millivolts. The power supply voltage is then quickly restored to ensure that no logic state changes are induced on the IC.
One proposed solution for testing ICs with a tester and probe card containing fewer signals and probes than the IC's number of bond pads, is to use the IEEE 1149.1 (also called JTAG) boundary scan standard for test access. This well-known test standard defines 1149.1-compliant ICs as having a TAP comprising 4 or 5 test pins, a TAP controller, and other on-chip circuitry including a digital shift register to convey logic signals to and from the non-test pins of the IC. One of the test pins, denoted TCK, is a test clock typically having a constant period (e.g., 100 ns). Although not described in 1149.1, if all non-test pins of the IC have both a driver and input logic buffer connected to them, regardless of whether they function as an input, output, or bi-directional pin, then structural integrity of each pin's driver and input buffer can be tested by performing a “wrap-around” test.
A wrap-around test consists of driving a pin to each logic value (0, 1), and then sampling the output of the input logic bu
Cuneo Kamand
Hollington Jermele
Killworth, Gottman Hagan & Schaeff LLP
LogicVision, Inc.
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