Method and circuit for synchronizing signals

Details Method and circuit for synchronizing signals Method and circuit for synchronizing signals

2003-07-10

2004-09-21

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S298000

Reexamination Certificate

active

06794910

ABSTRACT:

1. FIELD OF INVENTION
The invention relates to a method and circuit for synchronizing signals and, more particularly, to a method and circuit that synchronizes two signals triggered by clocks of different frequencies.
2. RELATED ART
As the design for integrated circuit (IC) is becoming more and more complicated, more and more designers are using electronic design automation (EDA) aiding tools in the designing process, to help finding any faults in advance and analyzing and optimizing the completeness of the testing samples, so as to reduce the waste of any redundant or unnecessary testing time, and to reduce the time required for development. Using this kind of aiding tools can help to design a circuit in which signals are triggered by clocks of the same frequency, to easily simulate and analyze the circuit to get a reliable result.
However, the designers still have to face the timing problems caused by signals triggered by clocks of different frequencies. For instance, in a camera using a 48 MHz advanced RISC machine (ARM), in order to achieve certain functionality, the circuit uses clocks of a higher frequency, such as 100 MHz. However, signals input to its sensor are synchronized with 13.5 or 27 MHz, but the corresponding circuit uses clocks of 27 MHz. Accordingly, this kind of timing problem cannot be simulated or analyzed by the EDA aiding tools to get a reliable result.
As shown in
FIG. 1
a
, a first module
11
operates at a lower frequency, uses a lower frequency clock LCK to process a write-enable signal WE, and transmits data in a first register
111
to a second module
12
. The second module
12
uses clocks of the higher frequency clock HCK to sample from the write-enable signal WE, in order to receive data transmitted from the first module
11
and store the data in a second register
121
of the second module
12
. When the write-enable signal WE has a high potential, that is, at the state of 1, the second module
12
can receive the data transmitted from the first module
11
and store the data into the second register
121
.
FIG. 1
b
shows a timing diagram of the write-enable signal WE and the higher frequency clock HCK in
FIG. 1
a
. The second module
12
samples the asynchronous write-enable signal WE when the clock is at state 1. Referring to
FIG. 1
b
, the second module
12
may miss the sampling result of the write-enable signal WE at the position due to an in sufficient set up time for the second module
12
to confirm the sampled write-enable signal WE. After a sufficient amount of time, at position b, the second module
12
can then successfully read the write-enable signal WE and thus enable the data write-in. When facing this kind of timing problems of clocks with different frequencies, the designers have to spend enormous amount of time to check each output result and to carry out fine tuning for the circuit, in order to meet the expected result. In addition, when facing the circuit design modification or procedure alteration, the designers must re-check and fine-tune the circuit design, which prolongs the time for development and design.
Therefore, it is an important subject of the invention to solve the above-mentioned timing problems when synchronizing two circuit modules triggered by clocks of different frequencies, so that analytical results of the EDA aiding tool are reliable, and the development time is reduced.
3. SUMMARY OF THE INVENTION
In view of the aforementioned problems, the object of the invention is to provide a method and circuit for synchronizing two signals triggered by clocks of different frequencies. This can resolve the timing problems caused by two signals triggered by clocks of different frequencies, so that circuit designer need not to spend too much time on solving timing problems, which reduces development time for circuit design.
Another object of the invention is to provide a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which can make the simulation analysis result of electronic design automation (EDA) aiding tool reliable.
In order to achieve the aforementioned objects of the invention, the method for synchronizing two signals triggered by clocks of different frequencies in accordance with the invention is to sample from a lower frequency write-enable signal at both positive and negative edges of a higher frequency clock. If the sampling result shows that the positive edge is at a low potential, which is at state 0, another sampling will be taken at the next negative edge. If the sampling result shows that the negative edge is at a high potential, which is at state 1, no sampling will be taken at the next positive edge. That is, if the sampling result is 1 for the positive or negative edge of the higher frequency clock, no sampling will be taken at the next opposite edge. If the sampling result is 0 for the positive or negative edge of the higher frequency clock, a sampling will be taken at the next opposite edge. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.
Furthermore, the circuit for implementing the aforementioned method for synchronizing two signals triggered by clocks of different frequencies includes a recording circuit and a sampling circuit. The recording circuit records states required for the positive and negative edges of the higher frequency clock. The sampling circuit samples at the opposite edges based on the states recorded in the recording circuit. It also joins the sampling results taken at the positive and negative edges to output a synchronized write-enable signal.
The recording circuit includes a first D-type flip-flop and a second D-type flip-flop, both are positive-edge triggered. The first D-type flip-flop records the states after sampling at the positive edge. The second D-type flip-flop records the states after sampling at the negative edge. The sampling circuit includes a first AND-gate, a third D-type flip-flop, a second AND-gate, a fourth D-type flip-flop, an OR-gate, and a fifth D-type flip-flop. The third D-type flip-flop, fourth D-type flip-flop and the fifth D-type flip-flop are all positive-edge triggered. The first AND-gate and the second AND-gate are used for controlling the lower frequency write-enable signal to be input to the third D-type flip-flop and the fourth D-type flip-flop. The third D-type flip-flop and the fourth D-type flip-flop are used for sampling from the lower frequency write-enable signal at the negative and positive edges. When the states of the first D-type flip-flop and the second D-type flip-flop are recorded as “lock states”, the output of the first AND-gate and the second AND-gate are also “0”. This means that the third D-type flip-flop and the fourth D-type flip-flop take no sampling operation, and the output result is also “0”. When the states of the first D-type flip-flop and the second D-type flip-flop are recorded as “sampling states”, the first AND-gate and the second AND-gate change their outputs in compliance with the lower frequency write-enable signal, and sample and output results through the third D-type flip-flop and the fourth D-type flip-flop. After that, the OR-gate joins and the sampling results taken at the positive and negative edges to output a synchronized write-enable signal. The fifth D-type flip-flop controls the conversion of the synchronized write-enable signal at the positive edge of the higher frequency clock. The higher frequency module can then sample the synchronized write-enable signal at the positive edge of the higher frequency clock to receive data transmitted from the lower frequency module.
According to the method and the circuit for synchronizing two signals triggered by clocks of different frequencies, the lower frequency write-enable signal generated by the first module and the higher frequency clock of the second module can be synchronized to generate a synchronized write-enable signal. After that, the second module uses the synchronized write-enable signal to trigger and receive dat

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