Method and circuit for suppressing sequential "zeroes" data

Details Method and circuit for suppressing sequential "zeroes" data Method and circuit for suppressing sequential "zeroes" data

1986-05-14

1988-04-26

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

358260, 455608, H04L 2700

Patent

active

047409940

ABSTRACT:
A method and a circuit for suppressing sequential "zeroes" data comprising, a transmitting portion and a receiving portion. The transmitting portion of the circuit provides a device for detecting whether zeroes data is sequenced in a frame, inserting the datum "1" after the sequential zeroes data when sequential zeroes data is detected, sending the frame having the datum "1" to the receiving portion and adding a portion of the frame, which is forced out by the insertion of the datum "1", to the top portion of the next frame. This forced out portion is used for detecting sequential zeroes data in the next frame. The receiving portion of the circuit detects whether the datum "1" has been inserted because sequential zeroes data are present in the frame received, and deletes the datum "1" from the received frame.

REFERENCES:
patent: 4027152 (1977-05-01), Brown et al.
patent: 4262309 (1981-04-01), Yamaguchi et al.
patent: 4347617 (1982-08-01), Murano et al.
patent: 4502143 (1985-02-01), Kato et al.

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