Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2000-06-05
2002-02-19
Kim, Robert H. (Department: 2882)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140AG, C348S308000, C348S301000
Reexamination Certificate
active
06348681
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to generation of control signals for an active pixel sensor cell array. More particularly, the invention pertains to methods and circuitry for generating “extended dynamic range” (XDR) reset pulses for causing each cell of an active pixel sensor cell array to operate with a piecewise linear transfer function.
DESCRIPTION OF THE RELATED ART
Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting photons incident at individual pixel sensor cells (of a pixel sensor cell array) into electrical signals indicative of the intensity of light energy incident at each cell. In general, a CCD uses a photogate to convert light energy incident at a cell into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, including high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. These weaknesses include limited readout rates and dynamic range limitations, and notably, the difficulty in integrating CCDs with CMOS-based microprocessors.
The expression “dynamic range” is used herein to denote the ratio of maximum detectable signal magnitude to minimum detectable signal magnitude. The present invention increases dynamic range of an active pixel sensor cell by increasing the maximum magnitude of the signal it can detect.
To overcome the limitations of CCD-based imaging circuits, imaging circuits have been developed which use active pixel sensor cells to convert light energy into electrical signals. An active pixel sensor cell typically includes a photodiode and a number of transistors which provide amplification, readout control, and reset control in addition to producing the electrical signal output from the cell.
FIG. 1
is an example of two identical CMOS active pixel sensor cells (
10
and
11
) having conventional design, connected along a column of an active pixel sensor cell array, and circuitry
20
for use in reading all cells connected along the column (and other columns not shown). As shown in
FIG. 1
, cell
10
includes photodiode d
1
(connected as shown between ground and Node
3
), and reset transistor N
1
. Transistor N
1
is an NMOS transistor whose drain is connected to a power supply node (Node
1
) maintained at potential Vcc, whose source is connected to Node
3
, and whose gate is connected to Node
2
. The gate of transistor N
1
is controlled (in a manner to be described below) by a RESET signal supplied to Node
2
. Alternatively, the reset transistor is a PMOS transistor.
Cell
10
also includes buffer transistor N
2
and row select transistor N
3
, each of which is an NMOS transistor. Transistor N
2
has a drain connected to Node
1
, a source connected to Node
4
, and a gate connected to Node
3
. Transistor N
3
has a drain connected to Node
4
, a source connected to Node
6
, and a gate connected to Node
5
. The gate of transistor N
3
is controlled (in a manner to be described below) by a ROW SELECT signal supplied to Node
5
. Node
6
is a column readout line, and the
FIG. 1
circuit typically includes several columns of cells, each having a column readout line.
As shown in
FIG. 1
, circuitry
20
includes detection and calculation circuit
21
. Circuit
21
has an input terminal connected to Node
6
, and other input terminals (not shown) connected to the column readout lines of the other columns of the cell array. Circuit
21
includes a sense amplifier for each column which outputs an analog voltage indicative of the light intensity incident at a cell along the column in response to voltages at Node
6
during a sampling period when each this cell is selected (typically, the sense amplifier outputs a sequence of analog voltages indicative of incident light intensity at each of a sequence of sequentially selected cells along the column). Circuit
21
typically implements correlated double sampling (“CDS”) on the voltage of each column readout line, typically performs post-processing on the output of each sense amplifier, and typically includes an analog-to-digital converter for generating digital data in response to the analog signal output from each sense amplifier (or from post-processing circuitry coupled to each sense amplifier). Circuitry
20
also includes a current mirror (comprising current source I
1
and NMOS transistors N
4
and N
5
connected as shown, and NMOS transistors identical to transistor N
5
for the other columns) which provides the necessary load for reading out the cells of the array.
In normal operation, circuit
21
receives a sequence of voltages at Node
6
(which node is common to all cells connected along the column), with each pair of consecutive voltages being indicative of light intensity incident at a different one of the cells along the column. Typically, circuit
21
receives a sequence of voltages from the column readout line of each column of cells, each pair of consecutive voltages on each column readout line being indicative of light intensity incident at a different one of the cells along a different column of the array. Circuit
21
typically includes a scan circuit which sequentially reads out analog signals indicative of light intensities of cells (of different columns) which are simultaneously generated (in parallel).
The operation of sampling (reading) each cell (e.g., cell
10
) begins by briefly pulsing the gate of the cell's reset transistor N
1
with a high level (relative to the bottom rail) of reset voltage “RESET.” This high level pulse of the reset voltage RESET (typically equal to Vcc, where Vcc is typically 5 volts) is a “full reset” signal (or “full reset” pulse or “full reset” potential) which resets the voltage on photodiode d
1
to an initial integration voltage to begin an image collection cycle.
Immediately after assertion of such full reset pulse of the voltage “RESET,” the initial integration voltage on photodiode d
1
(the voltage at Node
3
) is Vini=VRESET−VTN
1
−VCLOCK, where VTN
1
is the threshold voltage of transistor N
1
, VRESET is the high level of the voltage “RESET,” and VCLOCK is the voltage due to charge injection through transistor N
1
from the pulsed reset voltage (assumed to be constant). Vini also contains kT/C noise which is not constant over time. Similarly, the initial integration voltage at Node
4
is VRESET−VTN
1
−VCLOCK−VTN
2
, where VTN
2
is the threshold voltage of buffer transistor N
2
(functioning as a source follower).
Next, for a selected time period, photons are allowed to strike photodiode d
1
, thereby creating electron-hole pairs. The photogenerated holes are attracted to the ground terminal of photodiode d
1
, while the photogenerated electrons are attracted to the positive terminal of photodiode d
1
, each additional electron reducing the voltage at Node
3
. At the end of this image collection cycle, a final integration voltage will be present at Node
3
. The final integration voltage is Vf=Vini−VS=VRESET−VTN
1
−VCLOCK−VS, where VS represents the change in voltage (at Node
3
) due to the absorbed photons. Similarly, the final integration voltage at Node
4
is VRESET−VTN
1
−VCLOCK−VTN
2
−VS.
At the end of the image collection cycle, the gate of transistor N
3
is pulsed with a high level of row select voltage signal “ROW SELECT” to cause the voltage at Node
4
, which represents the final integration voltage of the cycle, to appear at Node
6
. A CDS circuit within detection and calculation circuit
21
samples the value of the final integration voltage as it appears at Node
6
.
Then, the gate of reset transistor N
1
is again pulsed briefly with a high level of reset voltage “RESET” (a “full reset” signal) which resets the voltage on photodiode d
1
to the initial integration voltage to begin another image collection cycle. Immediately after assertion of such full reset signal, the initial integration voltage at Node
4
is
Kindt Willem Johannes
Phan Christina
Segerstedt Brian
Girard & Equitz LLP
Kao Glen
National Semiconductor Corporation
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