Telecommunications – Receiver or analog modulated signal frequency converter – With particular receiver circuit
Reexamination Certificate
1999-05-21
2002-08-20
Hunter, Daniel (Department: 2684)
Telecommunications
Receiver or analog modulated signal frequency converter
With particular receiver circuit
C455S295000, C455S296000, C330S258000, C330S259000, C375S350000
Reexamination Certificate
active
06438366
ABSTRACT:
TECHNOLOGICAL FIELD
The invention relates generally to the technique of taking discrete samples from a signal, like a received signal at a radio frequency or intermediate frequency in a receiver. Especially the invention relates to reducing the inherent aliasing of noise in the sampling process.
BACKGROUND OF THE INVENTION
A transmitted radio signal contains some information modulated onto a radio frequency carrier. A multitude of radio receiver architectures are known for receiving the transmitted radio frequency signal and downconverting the received signal into baseband where the information content of the signal may be reconstructed. It is common to use a superheterodyne receiver which converts the received signal first into an intermediate frequency (IF), where some amplification and filtering is performed, and to apply a second downconversion from IF to baseband. Previously a direct conversion receiver has been proposed for reducing power consumption and decreasing the space taken by the components of the radio receiver.
FIG. 1
illustrates a known direct conversion receiver
100
, where a radio frequency signal picked up by the antenna
101
is filtered in a band pass filter
102
, which is also called a preselection filter, and amplified in a Low Noise Amplifier (LNA) or preamplifier
103
before mixing it into baseband simultaneously in two parallel mixers
104
and
105
. The mixers share a common local oscillator (LO)
106
but the LO signal is phase shifted by &pgr;/
2
radians in a phase shifter
107
before feeding it into one of the mixers to produce a pair of mutually phase shifted mixing results called the I and Q signals. The mixing result from each mixer is filtered in a low pass filter
108
or
109
before converting it into a stream of digital samples in an analogue to digital (A/D) converter
110
or
111
.
The drawbacks of the arrangement of
FIG. 1
are its inferior sensitivity compared to that of a corresponding superheterodyne receiver and LO leakage owing to the fact that the LO frequency is situated in the operational frequency band of the Low Noise Amplifier
103
and the preselection filter
102
.
FIG. 2
illustrates an alternative approach
200
to downconversion into baseband, known as subsampling. A radio frequency signal or an intermediate frequency signal is conducted along an input line
201
through a bandpass filter
202
to the input of a switch
203
. The output of the switch is coupled to the input of an amplifier
204
and to a capacitor
205
, the other end of the latter being connected to a reference potential, which is usually ground potential. The control signal
206
that controls the state of the switch
203
is a square wave coming from a local oscillator at a frequency which is either an integral multiple or a subharmonic of the radio frequency being downconverted. The frequency of the control signal is called the clock frequency or sampling frequency. The amplifier
204
acts as an output buffer. The arrangement of switch
203
and capacitor
205
is generally called an “switched-capacitor sampler” and will be denoted as an “SC sampler” from here on. The buffered output of an SC sampler on line
207
is a baseband signal. During the time interval when switch
203
is closed the SC sampler is said to be in tracking mode and during the time interval when switch
203
is open the SC sampler is said to be in hold mode.
One of the problems in an arrangement according to
FIG. 2
is the limited speed of the amplifier
204
. It is commonplace to use a CMOS amplifier because of the advantageous features inherent to CMOS technology. However, a known CMOS amplifier (when driven at a reasonable power level) is so slow to react to the changes in its input that the clock frequency of the arrangement must remain below 100 MHz. The SC sampler itself (the combination of a controllable switch and a capacitor) could operate at a much higher clock frequency.
The consequences of a relatively low sampling frequency are seen in the noise figure of the arrangement. The total noise figure NF
TOT
of a receiver front-end comprising an LNA and a subsampling arrangement according to
FIG. 2
can be expressed as
NF
TOT
=
B
N
f
N
NF
LNA
+
NF
mix
-
1
G
LNA
,
(
1
)
where B
n
is the equivalent noise bandwidth at the LNA output, f
n
is the Nyquist frequency of the sampler, NF
LNA
is the noise figure of the LNA, NF
mix
is the noise figure of the subsampling arrangement (also known as the subsampling mixer) and G
LNA
is the gain factor of the LNA. The first term in, (1) shows that to minimize the noise figure it is advantageous to limit the bandwidth before the sampler and maximize the sampling frequency. However, in an integrated circuit it may often be impossible or expensive to reduce B
n
sufficiently to prevent noise aliasing. In the second term of (1) the factor NF
mix
depends on the sampling frequency according to the formula
NF
mix
=
1
+
1
4
C
h
R
S
f
N
,
(
2
)
where C
h
is the capacitance of the sampling capacitor and R
S
is the source resistance of the subsampling mixer. In the derivation of (2) the usual assumption was made that the total noise power may be expressed as kT/C
h
. Although NF
mix
is typically high for subsampling mixers, it may be noted from equation (1) that it is divided by the preceding gain and therefore presents no fundamental limitation.
When a very fast slewing signal is sampled, the dynamic range of the subsampling mixer is degraded by timing uncertainty in the clock frequency. It can be shown that in the sampling-based conversion of a signal with frequency f, a jitter referenced to as t
j
limits the Signal-to-Noise Ratio (SNR) to
SNR
=
10
·
log
10
[
OSR
(
2
π
f
)
2
t
j
2
]
,
(
3
)
where the oversampling ratio OSR is defined as the ratio between the signal bandwidth and the sampler Nyquist frequency. Oversampling data converters are insensitive to jitter because their OSR is high and the signal frequency f is respectively low. On the contrary, a subsampling mixer always sees a relatively high input frequency f; increasing the sampling rate nevertheless reduces the effect of timing jitter because OSR is thus increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to bring forward a method and a circuit for downconverting an oscillating signal, the noise characteristics of the circuit being better than those of prior art solutions. A further object of the invention is that the presented method would be equally applicable to direct downconversion from radio frequency and to downconversion from intermediate frequency. A still further object if the invention is that the resulting circuit is efficient in terms of pwer consumption.
The objects of the invention are achieved by placing at least two SC samplers in parallel and using an amplifier to simultaneously buffer the outputs of the parallel SC samplers.
The electrical circuit according to the invention has an input and an output and is meant for
sampling an input signal coupled to the input having a certain input frequency and
converting the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It is characterised in that it comprises
a first sampler circuit coupled to the input,
a second sampler circuit coupled to the input,
a buffering component coupled to the output and
buffer switching means arranged to respond to a buffering command by coupling said first sampler circuit and said second sampler circuit to said buffering component.
The invention also concerns a receiver which is characterised in that it comprises in a sampling downconverter block:
a first sampler circuit coupled to the input of the sampling downconverter block,
a second sampler circuit coupled to the input of the sampling downconverter block,
a buffering component coupled to the output of the sampling downconverter block and
buffer switching means arranged to respond to a buffering command by coupling said first sampler circuit and said second sam
Halonen Kari
Lindfors Saska
Pärssinen Aarno
Hunter Daniel
Nokia Mobile Phones Limited
Perman & Green LLP
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