Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-02-28
2003-11-25
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S093000, C345S098000, C327S052000, C327S552000, C348S241000
Reexamination Certificate
active
06653992
ABSTRACT:
BACKGROUND AND SUMMARY
The invention relates to imaging devices, such as flat panel imagers. An imager is a device that receives electromagnetic radiation, e.g., light or x-rays, from the direction of something to be imaged in which an image is formed based the detected pattern of the radiation received at the imager. A flat panel imager is a type of imager that comprises a matrix/array of detection elements, with each detection element providing a separate item of image data that is usable to reconstruct an image. For light-sensitive imagers, each detection element comprises a photosensitive device. For x-ray sensitive imagers, each detection element comprises an x-ray sensitive device.
FIG. 1
depicts one configuration of electrical components for a flat panel imager, showing selectable wiring connections to transmit the voltage, current, or charge created by detection elements on the imager. Each image element
104
in the imager of
FIG. 1
comprises a photodiode
106
that generates an electrical signal in response to a light input. In an x-ray imager, the photodiode
106
receives light input from an x-ray scintillator element that generates light in response to x-rays. A transistor
108
(such as a thin-film N-type FET) functions as a switching element for the image element
104
. When it is desired to capture image data from image element
104
, control signals
114
are sent to gate driver
112
to “select” the gate of transistor
108
. Electrical signals from the photodiode
106
are passed through line
116
to a charge amplifier
110
. The output of charge amplifier
110
is sent to a “sample and hold” stage for further image processing/display. While
FIG. 1
only shows four image elements
104
a
-
104
d
, it is likely that the typical flat panel imager includes many such image elements
104
depending upon the size and resolution of the imaging device.
Many imagers perform simultaneous sampling of image data from multiple image elements in a correlated manner. For example, the imager of
FIG. 1
collects image data from an entire line of image elements (i.e., row or column) at the same time. To form an entire image frame, each line of image data is collected on a line-by-line basis until all lines for the image has been sampled. To obtain image data for a line of image elements, all the switching transistors (e.g.,
108
a
and
108
b
) for image elements (e.g.,
104
a
and
104
b
) on the same line are tied to the same control line
126
extending from gate driver
112
. When the image data for a particular line of image elements is desired, control signals
114
are sent to the gate driver
112
to select the transistor gates for the desired line of image elements. The electrical signals from the entire line of image elements are passed to their corresponding charge amplifiers, which output signal data to the subsequent sampling stage.
The photodiodes
106
of
FIG. 1
are connected to a common node
122
to supply a reverse bias voltage for the image element array. The gate driver
112
is connected to a node
124
to supply low gate voltage to drive the gate control lines. Parasitic capacitance may exist in the imager, such as C
gd
to the gate control line and C
ad
to the common array bias line for each image element. Each amplifier (
110
a
,
110
b
, etc.) may gain noise (e.g., AC noise) present on the low gate voltage and array bias voltage depending upon the ratio of the capacitances. If an entire line of image data is sampled at the same time, then the same noise offset may exist for every pixel in that line, which causes the corresponding line of pixels in the final image to appear markedly different from other lines of pixels. This type of “image artifact” is created in the example of
FIG. 1
because the low gate voltage and the array bias voltage are common for the amplifiers in the circuit. Compared to random pixel noise, this correlated noise is often relatively more visible and may significantly degrade image quality.
The present invention is directed to a method and mechanism for reducing correlated noise. According to an embodiment, the invention reduces correlated noise in imagers induced by noise in common supply voltages to the imager electronics, in which the reference input of each coordinated amplifier is connected to common voltage sources. An aspect of an embodiment is directed to coupling the reference input of differential amplifiers on the imager to common noise sources such as the imager low gate voltage and array bias voltage through suitably chosen capacitances. Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims.
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patent: 5589847 (1996-12-01), Lewis
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patent: 5739803 (1998-04-01), Neugebauer
patent: 5953060 (1999-09-01), Dierickx
patent: 6118438 (2000-09-01), Ho
patent: 6331844 (2001-12-01), Okumura et al.
patent: 6359607 (2002-03-01), Yanagi et al.
patent: 6469740 (2002-10-01), Kuroda et al.
Brailean, James C. et al.; “Noise Reduction Filters For Dynamic Image Sequences: A Review”;Proceedings of the IEEE; vol. 83, No. 9; Sep. 1995; pp. 1272-1292.
Colbeth Richard E.
Mollov Ivan P.
Bingham & McCutchen LLP
Dharia Prabodh
Shalwala Bipin
Varian Medical Systems Inc.
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