Method and circuit for reducing power and/or current...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S157000, C327S042000, C327S142000

Reexamination Certificate

active

06593785

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to a method and circuit for automatically reducing power consumption in a semiconductor device without the use of external logic or a dedicated pin.
2. Discussion of Related Art
Electrical products of today quite often incorporate semiconductor devices due to their many advantages. The use of such devices has enabled electrical products to accomplish tasks more quickly and efficiently than was previously possible. In an effort to continually improve such products, a desired goal has been to reduce the amount of power consumed during the operation of the products. Towards this end, it is desirable to reduce the power consumption of a product's component parts, including any semiconductor devices. One way to accomplish this goal is to “power down” the semiconductor device when the device is in a predefined state, such as an inactive state, so that the semiconductor device draws a reduced amount of current, and therefore, consumes less power.
One approach taken in the art to power down a semiconductor device is to pass a signal to the device over a dedicated pin or combination of dedicated pins, which signal directs the device to power down. A second approach taken in the art is to use a dedicated serial port or other communication scheme to direct a power down command word to the semiconductor device. The power down command word is then decoded, wherein the device is powered down. A significant problem with both of these approaches is that they require the use of at least one dedicated pin of the semiconductor device to accomplish the power down function. Oftentimes, a dedicated pin is unavailable because all of the pins on the semiconductor device are used to perform other functions. Thus, a “power down” mode cannot be implemented on such devices using prior technology. In addition, there are often situations where all existing input states of a semiconductor device are reserved for other functions. The effect of this situation is the same—no power down mode can be implemented on such devices using prior technology.
Accordingly, there is a need to provide a system for powering down a semiconductor device that minimizes or eliminates one or more of the problems set forth above.
SUMMARY OF THE INVENTION
The present invention provides a method and an apparatus for controlling a semiconductor device without the use of a dedicated pin. An advantage of such a system is that one may reduce current or power consumption in a semiconductor device that does not have a spare, dedicated pin, as may be required by conventional approaches. A method in accordance with this invention includes two main steps. The first step involves determining whether a detector input signal, corresponding to or derived from a device input signal, is invalid according to a predetermined parameter. The device is configured to perform a first predefined function, responsive to the device input signal, during normal operation. The second step involves generating, in response to the above determination, a function control signal configured to direct the semiconductor device to perform a second predefined function. The second predefined function is different from the first function. That is, an existing input signal used for one purpose in effect, is used for a second purpose. No dedicated signals, or terminals are required. The detector input signal may be derived directly from the device input signal, or it may be derived indirectly therefrom (e.g., by passing the device input signal through a buffer, PLL, or other structure).
In a preferred embodiment, the above-mentioned predetermined parameter is a minimum frequency associated with the detector input signal, and the second predefined function comprises reducing the power or current consumed by the semiconductor device (e.g., entering a “power down” mode). The function control signal thus may comprise a power down signal in a preferred embodiment. In operation, when the frequency of the detector input signal is less than the minimum frequency, the power down signal is generated which directs the semiconductor device to “power down,” or reduce current consumption in, at least one of its component circuits. By determining when the semiconductor device should be powered down based on a preexisting input signal to the device, rather than by using a dedicated pin to receive a dedicated “power down” input signal, a pin on the device may be preserved for other functions. Alternatively, the power down function may be implemented on a device which was previously incapable of such a function (due to pin limitations).
In another aspect of the present invention, an apparatus is provided which includes means for receiving a device input signal that performs a first predefined function during normal operation of the semiconductor device, and means for determining whether a detector input signal corresponding to the device input signal is invalid according to a predetermined parameter and generating in response thereto a function control signal to direct the semiconductor device to perform a second predefined function, wherein the second predefined function is different from the first predefined function. In a preferred, zero-delay buffer embodiment, the predetermined parameter is a minimum frequency associated with the detector input signal, and the second predefined function comprises reducing the power or current consumed by the zero-delay buffer (e.g., entering a “power down” mode). The function control signal may thus comprise a power down signal.
In a zero-delay buffer embodiment, the receiving means includes a pin on the buffer that is used for receiving an input signal as the device input signal. The device input signal is a signal already being used by the buffer to perform the first predefined function. For example, the device input signal may be an input clock signal. This input clock signal is used during normal operation, and is not dedicated exclusively for use in powering down the device. Also, the input clock signal is characterized by a minimum operating frequency, below which frequency the input clock signal may be considered to be invalid. The detector input signal is preferably directly derived from the device input (clock) signal, although, in alternative embodiments, the detector input signal is indirectly derived from the device input signal. The determining means includes a frequency detector in a preferred embodiment. The frequency detector determines whether the frequency of the detector input signal is less than the minimum frequency. If so, the frequency detector may generate the power down signal. In effect, the frequency detector may define a signal validity detector in a broader aspect of the present invention. For example, in other embodiments of the present invention, the means or circuit for determining signal invalidity of the detector input signal may alternately make such a determination based on such parameters as jitter, or phase lock (for PLL-based embodiments), or the like. An apparatus according to the present invention thus enables a semiconductor device to be powered down without the need for a dedicated pin.


REFERENCES:
patent: 3720841 (1973-03-01), Suzuki
patent: 3749936 (1973-07-01), Bell
patent: 3906258 (1975-09-01), Moe
patent: 3922526 (1975-11-01), Cochran
patent: 3971920 (1976-07-01), Johnson
patent: 4034301 (1977-07-01), Kashio
patent: 4144448 (1979-03-01), Pisciotta et al.
patent: 4293927 (1981-10-01), Hoshii
patent: 4341950 (1982-07-01), Kyles et al.
patent: 4404972 (1983-09-01), Gordon et al.
patent: 4467285 (1984-08-01), Rinaldi
patent: 4472821 (1984-09-01), Mazin et al.
patent: 4598214 (1986-07-01), Sexton
patent: 4615005 (1986-09-01), Maejima et al.
patent: 4633097 (1986-12-01), Dewitt
patent: 4686386 (1987-08-01), Tadao
patent: 4747057 (1988-05-01), DiGiulio et al.
patent: 4787097 (1988-11-01), Rizzo
patent: 4794628 (1988-12-01), Sakamoto et al.
patent: 4851987 (1989-07-01), Day

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