Method and circuit for reducing losses in DC-DC converters

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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Reexamination Certificate

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06930473

ABSTRACT:
In accordance with the present invention, a switching converter includes two transistors Q1and Q2parallel-connected between two terminals. Transistor Q1is optimized to reduce the dynamic loss and transistor Q2is optimized to reduce the conduction loss. Q1and Q2are configured and operated such that the dynamic loss of the converter is dictated substantially by Q1and the conduction loss of the converter is dictated substantially by Q2. Thus, the tradeoff between these two types of losses present in conventional techniques is eliminated, allowing the dynamic and conduction losses to be independently reduced. Further, the particular configuration and manner of operation of Q1and Q2enable reduction of the gate capacitance switching loss when operating under low load current conditions.

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