Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2006-07-10
2011-11-22
Phan, Huy Q (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010
Reexamination Certificate
active
08063655
ABSTRACT:
A regulated circuit having a number of metal-oxide-semiconductor field effect transistors (MOS FETs) and a method for using the same are provided to reduce Negative Bias Temperature Instability degradation of the MOS FETs on the circuit. In one embodiment, the method involves steps of: (i) detecting degradation in performance of at least one of the MOS FETs causing a shift in threshold voltage (VT) of the MOS FET; and (ii) if the shift in VTexceeds a predetermined value, forward biasing the MOS FETs, thereby reducing or reversing the shift in VT. Optionally, the method includes an initial step of determining if the circuit is in a non-dynamic operating mode before forward biasing the MOS FETs. Other embodiments are also disclosed.
REFERENCES:
patent: 5229311 (1993-07-01), Lai et al.
patent: 6071784 (2000-06-01), Mehta et al.
patent: 6144214 (2000-11-01), Athan
patent: 6455901 (2002-09-01), Kameyama et al.
patent: 6456104 (2002-09-01), Guarin et al.
patent: 6521469 (2003-02-01), La Rosa et al.
patent: 6762961 (2004-07-01), Eleyan et al.
patent: 6774462 (2004-08-01), Tanaka et al.
patent: 6815970 (2004-11-01), Rost et al.
patent: 6879177 (2005-04-01), Bolam et al.
patent: 6885105 (2005-04-01), Kakamu et al.
patent: 6933869 (2005-08-01), Starr et al.
patent: 7163886 (2007-01-01), Fujiwara et al.
patent: 7176522 (2007-02-01), Cheng et al.
patent: 7256087 (2007-08-01), Sadoughi et al.
patent: 7268575 (2007-09-01), Chen et al.
patent: 2005/0012122 (2005-01-01), Kakamu et al.
patent: 2006/0267621 (2006-11-01), Harris et al.
USPTO Notice of Allowance for U.S. Appl. No. 11/018,422 dated Apr. 16, 2007; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/018,422 dated Dec. 1, 2006; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/018,422 dated Jul. 21, 2006; 12 pages.
USPTO Requirement Restriction for U.S. Appl. No. 11/018,422 dated May 8, 2006; 5 pages.
Pohland Oliver
Puchner Helmut
Cypress Semiconductor Corporation
Phan Huy Q
Vazquez Arleen M
LandOfFree
Method and circuit for reducing degradation in a regulated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and circuit for reducing degradation in a regulated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for reducing degradation in a regulated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4288072