Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2000-03-27
2001-10-16
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S00100A, C331S008000, C331S014000, C327S156000, C327S157000, C327S159000, C327S111000
Reexamination Certificate
active
06304147
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to charge pump circuits for use in phase locked loops. More specifically, the present invention relates to a reduced power state of a charge pump circuit.
BACKGROUND OF THE INVENTION
Timing circuits are a core portion of communication systems. Timing circuits are used to generate signals, to decode signals, and to synchronise circuits generating and sending signals and those circuits receiving and decoding those signals. In this fashion, a synchronous communication network proceeds with substantial efficiency of signal rate vs. clock rate.
Phase locked loop circuits are a common solution to synchronising two signals and for frequency synthesis to generate a local oscillation in transceiver circuits. They are used in many different applications, such as in communication and networking systems. For example, microprocessor chips require on-chip clock generation. A phase locked loop enables a precise tracking and.phase locking of a synthesized clock signal to a reference clock signal.
Some prior art phase locked loops operate based on analog algorithms. Such systems are subject to very large phase errors and are heavily influenced by random noise. Because of the analog nature of such systems they are difficult to highly integrate. Also, functions such as a divide by N or edge registration are difficult to implement in an integrated device. Analog systems are also relatively susceptible to loss of phase lock or incapability of obtaining phase lock because of random variations in the system.
Other prior art phase locked loops operate based on digital algorithms. One such phase locked loop (PLL) is identified as MT9042B available from Mitel Corporation and is described in detail in Issue 11 of their publication “Digital Switching & Networking Components”. If network synchronization is temporarily disrupted, the MT 9042B provides timing and synchronization signals based on storage techniques. The stored values are determined during synchronized mode when an external reference signal is available and the clock is locked to the external reference signal. When the external reference signal is lost, the stored values are used to attempt to maintain the output clock signal.
Because of the widespread use of wireless communications, it is desirable to reduce power consumption of timing circuits. For example, in U.S. Pat. No. 5,933,031 in the name of Konmo a clock signal generating device is disclosed having an which the phase frequency detector outputs—UP and DOWN—are forcibly set to opposite values. This reduces power consumption when the two signals would otherwise be a same value.
In U.S. Pat. No. 5,783,972 in the name of Nishikawa, another power saving PLL circuit is presented. According to the disclosure, a charge pump circuit is provided with a plurality of different current sources for each of the UP and DOWN output ports. This allows for lower power operation of the charge pump when variations in phase frequency are small. Since this is the most common occurrence in a stable communication system, the overall PLL power consumption is reduced. That said, the proposed circuit requires several current sources for each output port and, as such, is more complicated than previously used circuits.
In U.S. Pat. No. 5,598,405 in the name of Hirose, another power saving circuit is presented. Here the phase control loop is only “turned on” preceding each transmission time slot and each reception timeslot. As such, when only a few of several time slots are used, the phase control loop is enabled less than all the time. This results in power savings.
It is an object of the present invention to provide a PLL for consuming less power than a simple prior art PLL circuit while providing similar functionality.
SUMMARY OF THE INVENTION
According to the invention a charge pump circuit is provided that consumes a reduced amount of power when neither an “UP” nor a “DN” signal is being provided. Preferably, the charge pump circuit is provided with a reasonable setup time so that operation of the phase locked loop is not affected by the reduced power consumption mode of operation.
In accordance with the invention there is provided a charge pump circuit for use with a phase locked loop. The circuit includes: an input port for receiving a signal indicative of a misalignment between two clock signals; an output port; a circuit for providing a drive signal at the output port when the comparison result is indicative of misalignment of the signals and for providing high impedance at the output port when the comparison result is indicative of alignment of the signals; and, a circuit for entering a sleep mode to reduce power consumption of the charge pump when providing a high impedance at the output port.
In accordance with another embodiment of the invention there is provided a charge pump phase locked loop circuit comprising: a voltage controlled oscillation circuit for receiving a drive signal and for providing a clock signal having an oscillation frequency controlled in dependence upon the drive signal; a phase frequency discriminator for receiving a reference signal and for comparing phases of a first signal derived from the clock signal and the reference signal with each other and for providing a comparison result indicative of phase alignment of the signals; and, a charge pump circuit comprising an output port and for providing the drive signal at the output port when the comparison result is indicative of misalignment of the signals and for providing high impedance at the output port when the comparison result is indicative of alignment of the signals, the charge pump circuit comprising logic for entering a sleep mode to reduce power consumption of the charge pump when providing a high impedance at the output port.
In accordance with another embodiment of the invention there is provided a charge pump circuit having an output port for use with a phase locked loop comprising the steps of: receiving a signal indicative of a misalignment between two clock signals; providing a drive signal at the output port when the comparison result is indicative of misalignment of the signals; providing high impedance at the output port when the comparison result is indicative of alignment of the signals; and, when providing a high impedance at the output port, causing the charge pump to enter a sleep mode to reduce power consumption of the charge pump.
REFERENCES:
patent: 4814726 (1989-03-01), Byrd et al.
patent: 5475326 (1995-12-01), Masuda
patent: 5598405 (1997-01-01), Hirose
patent: 5783972 (1998-07-01), Nishikawa
patent: 5847614 (1998-12-01), Gilbert et al.
patent: 5933031 (1999-08-01), Konno
patent: 5986487 (1999-11-01), Ridgers
Koninklijke Philips Electronics , N.V.
Lacasse & Associates
Mis David
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