Method and circuit for recovering a clock

Details Method and circuit for recovering a clock Method and circuit for recovering a clock

2005-04-02

2008-09-23

Barnie, Rexford (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

C369S053340

Reexamination Certificate

active

07427934

ABSTRACT:
The present invention relates to a method for recovering a clock from a run-length-coded data stream, said method making it possible for a phase-locked loop to lock in a rapid manner, and also to a circuit for implementing the method. An inventive method for recovering a clock from a run-length-coded data stream comprises the steps of: ascertaining the distribution of symbol lengths in the data stream for a chosen clock period; determining the deviation of the maxima of the distribution of symbol lengths from integer multiples of the chosen clock period; and regulating the chosen clock period on the basis of the deviation determined.

REFERENCES:
patent: 4495474 (1985-01-01), Meisei et al.
patent: 6954413 (2005-10-01), Graffouliere
patent: 2001/0055355 (2001-12-01), Okamoto
patent: 2005/0281292 (2005-12-01), Troulis et al.
patent: 195 46 632 (1997-06-01), None
patent: 0763824 (1997-03-01), None
Seok Jun Ko et al: “A Robust Digital Timing Recovery With Asymmetry Compensator for High Speed Optical Drive Systems” IEEE Transations on Consumer Electronics, IEEE Inc. New York US, vol. 47, No. 4, Nov. 2001, pp. 821-830.
Search Report Dated Jun. 1, 2005.

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