Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-09-12
2003-02-25
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S233100
Reexamination Certificate
active
06525961
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention generally relates to programming nonvolatile memory, and more specifically to a method and a circuit for programming a multilevel nonvolatile memory.
2. Description of Related Art
A memory chip is an electronic part which is used by a computer to store a program or data. There are two basic types of memory chips, volatile memory chips and nonvolatile memory chips. A nonvolatile memory chip, such as an EPROM or flash memory, does not lose its contents when power is switched off, while a volatile memory chips loses its contents when power is removed. It is known that most recent developments in the field of nonvolatile memories are directed towards increasing the storage capacities thereof.
Programming of a nonvolatile memory cell includes applying a potential difference between the drain and source of the floating gate transistor of the memory cell in the presence of a high potential difference being applied between the control gate and the source of the floating gate transistor. A known method used to program a multilevel nonvolatile memory utilizes a “voltage ladder” circuit, which is generated entirely inside the memory device. Moreover, in order to achieve effective programming, certain pins are dedicated for programming the memory cells. This limits the future expansion of the memory which generally requires an increasing number of address pins. Conventional memories use a chip enable pin Cen as a synchronization signal for the programming operation. However, the chip enable pin Cen may not be available in some nonvolatile memory devices for synchronizing programming operations.
In addition, the duration of time for programming the memory cells (i.e., the time for applying the programming voltages to a nonvolatile memory cell to the desired logic state) typically depends on complicated internal clock circuits whose delays are process dependent and varies considerably among individual devices.
Based upon the foregoing, there is a need for more effectively programming a multilevel nonvolatile memory device.
SUMMARY OF THE INVENTION
The present invention satisfies a significant need for more efficiently programming a multilevel nonvolatile memory. In accordance with an exemplary embodiment of the present invention, a multilevel nonvolatile memory is capable of being programmed without the use of dedicated programming pins. In addition, the memory does not require internal clock generation circuits to provide synchronization during a programming operation. Instead, the nonvolatile memory utilizes one or more address pins for providing synchronization during a programming operation.
A method of programming a nonvolatile memory cell according to the exemplary embodiment of the present invention may including comparing, using at least one address pin of the memory, a data value stored in an addressed nonvolatile memory cell to a desired data value, and applying, using the at least one address pin, program voltages to the addressed nonvolatile memory cell based upon the comparison.
REFERENCES:
patent: 5959883 (1999-09-01), Brennan et al.
patent: 6178118 (2001-01-01), Lin et al.
patent: 6339545 (2002-01-01), Banks
patent: 2 632 110 (1989-12-01), None
patent: 05133142 (1994-12-01), None
Montanaro Massimo
Oddone Giorgio
Rolandi Paolo
Jenkens & Gilchrist P.C.
STMicroelectronics S.r.l.
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