Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-06-29
2009-08-18
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185250, C365S189090, C365S203000
Reexamination Certificate
active
07577033
ABSTRACT:
Disclosed is a method and semiconductor circuit for providing a read operation in a NAND flash memory. The NAND flash memory includes an array of bit lines. The method includes selecting a first set of bit lines of the array of bit lines for performing the read operation. The first set of bit lines are pre-charged to a pre-defined voltage level. At the same time, a second set of bit line are also charged to the pre-defined voltage. The second set of bit lines are in anti-phase to the first set of bit lines. Further, reading of the first set of bit-lines is performed. The second set of bit lines is maintained at the pre-defined voltage level during the reading of the first set of bit lines.
REFERENCES:
patent: 5999451 (1999-12-01), Lin et al.
patent: 2008/0062762 (2008-03-01), Doyle
patent: 2008/0159032 (2008-07-01), Lin
Tanaka, Tomoharu et al. “a Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory”, IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994; 12 pages.
Grossman Tucker Perreault & Pfleger PLLC
Intel Corporation
Le Thong Q
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