Method and circuit for optimizing power efficiency in a...

Details Method and circuit for optimizing power efficiency in a... Method and circuit for optimizing power efficiency in a...

2005-08-23

2005-08-23

Vu, Bao Q. (Department: 2838)

Electricity: power supply or regulation systems

In shunt with source or load

Using choke and switch across source

C323S284000, C323S274000, C323S282000

Reexamination Certificate

active

06933706

ABSTRACT:
In one embodiment, a turn-on delay control structure (30) includes a sense FET device (31) that is coupled to a switch node (13) in a synchronous DC-DC converter (10). The DC-DC converter includes a high-side switch (11) and a low-side switch (12). The sense FET device (31) senses current conduction in a body diode (18) of the low-side switch (12). A current sensing/comparator circuit (32) coupled to the sense FET (31) detects changes in current conduction. A delay circuit (33) and a clock/logic circuit (32) coupled to the current sensing/comparator circuit (32) predict and adjust delay time in switching between the high-side switch (11) and the low-side switch (12).

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