Method and circuit for optimizing power consumption and...

Details Method and circuit for optimizing power consumption and... Method and circuit for optimizing power consumption and...

2002-11-04

2004-05-11

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110, C365S189090

Reexamination Certificate

active

06735145

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to driver circuits, and more particularly to a method and circuit for optimizing power consumption and performance of driver circuits.
BACKGROUND OF THE INVENTION
Low power requirements in a circuit often conflict with high performance requirements. As a result, the voltage ranges at which circuits can operate can be limited in order to address this conflict. For example, circuit configurations that are efficient with regard to power, performance, and area are limited in that they can operate at one voltage but often cannot operate properly at other voltages, e.g., lower voltages. Conversely, circuit configurations that are designed for broad voltage operations often do not exhibit optimal power, performance, and area characteristics.
A classic example of the trade off between low power requirements and high performance requirements is that of a register file. A register file often includes an array of memory elements. All memory elements within a bit slice are connected to one another through a multiplexor. Each memory element within a bit slice could include, for example, one or more pass gates, each associated with a different word line. The multiplexor is effectively distributed by incorporating the pass gates in each memory element and then coupling the pass gate outputs together within the bit slice.
FIG. 1
is a block diagram of a conventional file register circuit
10
, which includes a conventional wordline driver
12
, an NFET transistor
14
, a PFET transistor
16
, a bit line
18
, and a memory
20
. To compensate for the adverse effects of an NFET only configuration as described above, the PFET transistor
16
is placed in parallel with the NFET transistor
14
making a transmission gate. As described above, NFET transistors are known to pass good logical 0s but poor logical 1s. In contrast, PFET transistors are known to pass good logical 1s but a poor logical 0s. When an NFET transistor and a PFET transistor work in tandem, the result is the passing of good logical 1s and good logical 0s. Generally, the NFET transistor does the majority of the work. On an upswing (i.e., a logical 0 to a logical 1), the NFET transistor charges up a node quite quickly but only part way. The PFET transistor takes the node up the rest of the way resulting in a logical 1. Conversely, when trying to swing the signal in the other direction (i.e., a logical 1 to a logical 0), the NFET transistor does all the work. The PFET transistor helps but not significantly.
Problems with circuit configurations using an NFET/PFET (N/P) transistor pair configuration are as follows. First the area required increases, e.g., at least doubles, because of the area required by the complementary PFET transistors. Second, two different control signals are required. There is a positive active control signal to activate each NFET transistor and a negative active control signal to activate each PFET transistor. Furthermore, implementing the PFET transistors increases the power consumption. Third, the additional PFET transistors increase the power consumption.
An NFET only configuration is preferred for various applications, such as register files and memories, which generally have tight area and power constraints. NFET transistors enable the building of complex functions in a minimum amount of area. NFET transistors also use a minimum amount of power.
With regard to area, NFET only configurations require only one control line and one control line driver. If, for instance, PFET transistors were also used a second control line and a second control line driver would be required. Using only NFET transistors also reduces power and area because complement signals for the PFET transistors are not required. The bit line capacitance is also reduced, thereby reducing bit line power.
NFET only configurations have reduced bit line voltage swings resulting in lower bit line power. The bit line voltage swing is the power supply voltage (Vdd) minus the device's threshold voltage (Vt. The lower bit line power is due to the bit line power being directly proportional to the voltage squared. Hence, power and area are optimized using the NFET only configuration.
A problem with an NFET only configuration, however, is that NFET transistors are notorious for not passing good logical 1s. For example, with a logical 1 applied to its drain or source and a logical 1 of the same magnitude applied to its gate, the resulting output voltage at the other side of that pass transistor is a logical 1. However, it is a logical 1 that is at a reduced voltage. A circuit receiving this output voltage must be designed to handle the reduced voltage. The reduced voltage is the total gate voltage minus Vt.
As Vdd drops, the amount of gate overdrive (Vdd−Vt) is reduced. As Vdd drops and starts to get closer to Vt, the NFET transistor will not pass a sufficiently high output voltage to provide a logical 1. For example, if Vdd is 2.5V and Vt is 0.5V, the transistor's output voltage can be expected to be 2 volts. However, if Vdd is 1V and Vt is 0.4V, the transistor's output voltage can be expected to be only 0.6V. Accordingly, as Vdd continues to be reduced, the delta between Vdd and Vt becomes lower and lower.
Consider a bit line multiplexor that couples together the NFET transistors of a bit slice. Because the output of the bit line multiplexor is a function of both Vdd and the Vt of the NFET transistors, there is reduced headroom as Vdd is reduced. Hence, as Vdd is reduced, the operation of the circuit is compromised both by a rapid degradation in performance and even functional integrity. One solution is to utilize a bootstrap circuit with an NFET only configuration.
FIG. 2
is a block diagram of a conventional file register circuit
30
, which includes a word line driver
32
, a conventional bootstrap circuit
34
, an NFET transistor
36
, a bit line
38
, and a memory
40
. The conventional bootstrap circuit
34
enables the wordline driver to drive a higher voltage at the gate of the NFET transistor
36
. If there is a higher voltage at the gate, the gate voltage minus Vt is still substantially equal to Vdd.
A problem with the conventional bootstrap
34
circuit is that the voltages are elevated at the gate all the time in order to achieve higher performance. Accordingly, while the conventional bootstrap circuit
34
may address the problem of area, the conventional bootstrap circuit
34
does not address the problem of power consumption. As a result, such circuits consume excess power. Accordingly, the known solutions either consume too much power and area, under-perform, or operate within a narrow voltage range.
Accordingly, what is needed is a method and circuit for optimizing the power consumption and performance of driver circuits. The method and system should provide a driver circuit that enables other circuits to operate over broad voltage ranges without compromising power consumption and performance. The present invention addresses such a need.
SUMMARY OF INVENTION
An enhanced driver circuit is disclosed. Embodiments of the present invention include an enhanced driver that provides a first voltage. A detector coupled to the enhanced driver monitors the first voltage. If the first voltage falls below a predetermined value, the enhanced driver increases the first voltage to at least an optimal voltage.
In another aspect of the present invention, the enhanced driver includes a programmable bootstrap circuit that selectively provides a second voltage to replace the first voltage if the first voltage falls below the predetermined value. The value of the second voltage can be anywhere between the predetermined value and the original value of the first voltage, or higher.
According to the method and system disclosed herein, the embodiments of present invention provide a programmable bootstrap circuit. Consequently, an enhanced driver circuit is provided that increases the voltage range at which circuits driven by the enhanced driver circuit can operate without compromising the

Affiliated with

Also associated with

Rating

Method and circuit for optimizing power consumption and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit for optimizing power consumption and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for optimizing power consumption and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3228695