Method and circuit for normalization of floating point...

Details Method and circuit for normalization of floating point... Method and circuit for normalization of floating point...

2005-12-27

2005-12-27

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S205000

Reexamination Certificate

active

06981012

ABSTRACT:
The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

REFERENCES:
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patent: 5771183 (1998-06-01), Makineni
patent: 5831884 (1998-11-01), Suzuki
patent: 6175847 (2001-01-01), Brooks et al.
patent: 6178437 (2001-01-01), Dhong et al.
patent: 6499044 (2002-12-01), Brooks et al.
patent: 6557021 (2003-04-01), Brooks et al.

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