Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2002-09-13
2004-08-10
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S025000, C331S175000, C327S157000
Reexamination Certificate
active
06774731
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method and a circuit for minimizing glitches in phase-locked loops.
BACKGROUND OF THE INVENTION
A PLL (Phase Lock Loop) as generally shown at
1
in
FIG. 1
comprises essentially a phase comparator
2
, a filter
3
, a frequency divider
4
, and a voltage controlled oscillator VCO
5
. With the phase lock loop PLL
1
locked to a periodic input signal at a frequency Fref, a frequency Fvco of the voltage controlled oscillator VCO
5
is equal to that of the input signal multiplied by a division ratio N of the frequency divider
4
.
The phase comparator
2
then generates a signal which is proportional to the phase difference between the input signal and the output signal of the frequency divider
4
. This signal modifies, through the filter
3
, the control voltage of the voltage controlled oscillator VCO
5
, and consequently its frequency Fvco as well, thereby bringing the output frequency Fdiv of the frequency divider
4
to the same value as the input frequency Fref.
The characteristic parameters according to which a phase lock loop PLL
1
is evaluated are:
accuracy of the generated frequency;
phase noise;
glitch rejection;
locking time; and
loop phase margin.
The frequency accuracy of the voltage controlled oscillator VCO
5
is dependent on the frequency accuracy of the input signal and the accuracy of the phase comparator
2
.
Specifically, it is:
&Dgr;
Fvco=N*&Dgr;Fref
+&Dgr;&PHgr;/2
*&pgr;*Fvco
(1)
where,
&Dgr;Fvco is the frequency error of the voltage controlled oscillator VCO
5
;
N is the division ratio of the frequency divider
4
;
&Dgr;Fref is the frequency error of the input signal;
&Dgr;&PHgr; is the phase error of the phase comparator
2
; and
Fvco is the output frequency of the voltage controlled oscillator VCO
5
.
System specifications covering certain communication standards provide for the largest frequency error of the voltage controlled oscillator VCO
5
to be in the 10
−8
*Fvco range. For example, the GSM Standard sets the maximum error to 2*10
−8
*Fvco.
In this case, assuming one half of that frequency error to be due to inaccuracy of the input frequency (usually obtained from a crystal oscillator), the maximum acceptable phase error would be 6*10
−8
radians.
Such a restricted value for the phase error rules out the use a Gilbert cell for a phase comparator, since this cell exhibits a minimum phase error which lies well above said limit. Furthermore, a Gilbert cell type of phase comparator would exhibit a non-constant system loop gain in the phase locked range of operation.
Thus, for standard practical applications, the phase comparator is provided in a charge pump form, using first Icharge and second Idischarge current generators, having the same Icp value and opposite signs, which generators will vary the output control voltage in opposite directions according to whether the output signal of the frequency divider
4
is leading or lagging behind the input signal. A block diagram for a phase lock loop PLL
1
′ including a charge pump
6
, according to the prior art, is shown in FIG.
2
.
To avoid phase errors and variations in the loop gain of the phase lock loop PLL
1
′ near the locking range, a time interval Tmin is usually provided when both current generators, Icharge and Idischarge, deliver equal and opposite currents, such that the input voltage to the filter
3
will remain unchanged, as shown in FIG.
3
. Thus, the current generators Icharge, Idischarge are turned on at each cycle to ensure that the frequency of the voltage controlled oscillator VCO
5
remains locked to the value N*Fref.
The use of a filter
3
′ with two-poles and a zero, as schematically illustrated in
FIG. 4
, is conceivable. This filter
3
′ comprises a resistive element R
1
connected in series to a first capacitive element C
1
, between a terminal T
1
and a voltage reference such as a ground GND. The filter
3
′ also comprises a second capacitive element C
2
, connected between said terminal T
1
and ground, in parallel with said resistive element R
1
and said first capacitive element C
1
.
The settling time is dependent on the overall loop gain, its phase margin, the filter size, and the maximum admissible frequency error.
Using the filter
3
′, it is readily seen that the proportionality of the settling time Ts is:
T
s
∝
N
*
R1
*
C1
I
cp
*
K
o
*
ln
(
B
Δ
F
max
)
(
2
)
where,
N is the division ratio;
R
1
, C
1
are elements of the filter
3
′;
Icp is the charge pump
6
current;
Ko is the oscillator VCO
5
gain;
B is the channel jump of the oscillator VCO
5
;
&Dgr;Fmax is the maximum frequency error of the oscillator VCO
5
.
Formula (2) shows that to obtain short settling times, as is normally required, in wide band, small frequency error systems, it is necessary to use very high values for the charge pump
6
current and filters having decidedly small time constants.
Reasonable values for conventional systems of the GSM and DCS types are:
Icp=4 mA, and
t=25 &mgr;s.
Thus, by suitable dimensioning of the filter and the charge pump, a phase lock loop PLL could be provided with a settling time value according to specification. However, such dimensioning would be at variance with the specified rejection of glitches at frequencies that are multiples of the reference frequency Fref of the phase lock loop PLL
1
.
In fact, a real phase look loop PLL
1
would exhibit, as a result of process tolerances, a non-pure frequency spectrum, like that shown in FIG.
5
.
In particular, the two most evident glitches locate a distance equal to the reference frequency Fref away from the lock frequency Fvco of the voltage controlled oscillator VCO
5
. Other glitches, located farther from the oscillation frequency Fvco, are filtered and reduced to a large extent.
It should be noted that glitches are mainly due to two different phenomena, namely the leakage current of the VCO control terminal and a dissymmetry between the two generators of the charge pump.
In particular, the leakage current of the VCO control node is the sum of the leakage currents of the charge pump and the VCO. The contribution from the latter is generally dominant because, at the frequencies of interest, the VCO would essentially consist of an LC resonator, wherein the frequency variation is obtained by varying the voltage across a junction capacitance which has a fairly large leakage current.
The overall leakage current causes the control voltage of the VCO to change proportionally to that current, even with the VCO in the locked state, during the “off” period of the current generators of the charge pump. Consequently, at each cycle, the charge pump is to balance the amount of charge lost during the “off” period.
Thus, the control voltage waveform shows a periodic trend with a period 1/Fref, and this periodic signal generates glitches at frequencies that are multiples of the reference frequency Fref. It can be seen, therefore, that the amplitude of such glitches is directly proportional to the leakage current and inversely proportional to the value of the second capacitive element C
2
of the filter
3
′.
As a result, in transmission systems designed to strict specifications as to settling time and glitches, this contribution to the overall glitch requires that VCOs with very low associated leakage values be used. There are VCOs commercially available which meet both specifications for conventional transmission systems.
The generation of glitches is also due to asymmetry of the two generators of the charge pump. Particularly in the locked condition, in order to prevent the frequency of the VCO from varying, the average voltage value at the control node must be kept constant. The amounts of charge supplied by the two current generators must, therefore, be equal and opposite.
Assuming that in the locked condition one of the generators is delivering a current
D'Aquila Alessandro
Gramegna Giuseppe
Magazzu Antonio
Marletta Benedetto Marco
Iannucci Robert
Kinkead Arnold
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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