Multiplex communications – Wide area network – Packet switching
Reexamination Certificate
1999-11-02
2004-01-27
Ton, Dang (Department: 2661)
Multiplex communications
Wide area network
Packet switching
C370S242000, C370S244000
Reexamination Certificate
active
06683890
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to the field of synchronous digital transmissions and in particular to a method and implementation circuit that permit of improving the pointer processing in the event of payload contiguous concatenation in synchronous digital hierarchy (SDH) frames.
2. Description of the Prior Art
The Synchronous Digital Hierarchy (briefly, SDH) is known since the end of the Eighties and it will not be described in greater detail being considered as known to a person skilled in the art. The synchronous transport modules STM-N (N=1, 4, 16, 64) are characteristic features of the SDH transmission.
In view of the need to transport a lot of information, the payload of various frames can profitably be contiguously concatenated. The problem that payload contiguous concatenation has up to now been faced with is described in the following Recommendations: ITU-T G.707, ITU-T G.783 “Characteristics of Synchronous Digital Hierarchy (SDH) equipment functional blocks”, Annex C—Algorithm for pointer detection (hereinafter referred to as Doc.1), and ETS300 417-1-1, January 1996, “Transmission and Multiplexing (TM); Generic functional requirements for Synchronous Digital Hierarchy (SDH) transmission equipment; Part 1-1: Generic processes and performance, Annex B (normative): Pointer interpretation (pages 102-105), (hereinafter referred to as Doc.2) which, to all intents and purposes, are intended to be an integral part of the present description, and as such are incorporated herein in their entirety by reference.
Docs. 1 and 2 show two different state diagrams to be used with the algorithm for pointer processing in case of concatenated payload or in case of non-concatenated payload. On the other hand, there is not disclosed any solution for automatically going from the states of one diagram to the other. Therefore, it is necessary to provide for a switch that permits of configuring the circuit in one of the two conditions.
SUMMARY OF THE INVENTION
A primary object of the present invention is to solve the above mentioned problem, and thus provide a means for automatically transitioning between the states of one diagram and those of another diagram.
The present invention provides a method and a circuit which can be represented through a state diagram containing therein both the diagrams contemplated by the Standards but which, through the introduction of one or more intermediate states and the special processing of data from individual pointer processors, does not require the prior configuration of the operation. Two different exemplary embodiments will be described in detail, with the first being extremely modular.
REFERENCES:
patent: 5539750 (1996-07-01), Kivi-Mannila et al.
patent: 5724342 (1998-03-01), Sihvola et al.
patent: 6094440 (2000-07-01), Sugawara et al.
Andrew S. Tanenbaum, Computer Networks, 1996, Prentice Hall PTR, Third Edition, pp. 125-130.*
Recommendations: ITU-T G.707 (3/96).
Recommendations: ITU-T G.783 “Characteristics of Synchronous Digital Hierarchy (SDH) equipment functional blocks”, Annex C-Algorithm for pointer detection.
ETS300 417-1-1, Jan. 1996, “Transmission and Multiplexing ™ Generic functional requirements for Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes and performance”.
Bellato Alberto
Cabrini Sergio
Girardi Claudio
Lometti Alberto
Razzetti Luca
Alcatel
Sughrue & Mion, PLLC
Ton Dang
Wilson Robert W.
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