Method and circuit for improved timing and noise margin in a DRA

Details Method and circuit for improved timing and noise margin in a DRA Method and circuit for improved timing and noise margin in a DRA

1993-03-26

1995-01-03

Gross, Anita Pellman

Static information storage and retrieval

Addressing

36523008, 365194, G11C 800, G11C 700

Patent

active

053792610

ABSTRACT:
A method and circuit improves the timing of a static column mode device by extending the valid write time to be equal to the write time in a fast page mode device. In particular, the circuit extends the global write enable signal and maintains the address in the address latch to increase the valid write time. Also, the circuit of the present invention improves the noise margin in the static column mode device by decoupling the write enable and column address strobe signals after they are initially received to ignore any noise in those signals. A timer is used.

REFERENCES:
patent: 4476548 (1984-10-01), Matsumoto
patent: 4984216 (1991-01-01), Toda
patent: 5077693 (1991-12-01), Hardee
patent: 5079748 (1992-01-01), Miyatake
patent: 5280601 (1994-01-01), Desai
Microelectronic Circuits, 2nd Edition A. S. Sedra, K. C. Smith, HRW, Inc., New York, 1987.

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