Method and circuit for generation of digitally frequency-shiftab

Telegraphy – Systems – Printing

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178 66A, 340171R, H04B 104

Patent

active

040830080

ABSTRACT:
A first counter operating as a frequency-shiftable frequency divider is caused to reset before its normal count recycle in one setting of a flip-flop to reduce the factor of frequency division in response to a keying signal. A second counter, operating on a digital input derived from the output of the frequency-shiftable divider sequences a logic network to produce a stepped wave output, with steps each of a duration of one or two count intervals sequentially connecting voltage at one of four several non-zero predetermined voltage levels in a predetermined sequence to the output. The stepped wave approximates a succession of half-wave sinusoids of the same polarity in which the bottom step of zero voltage is of zero width so that the last next lowest step of one sinusoid and the first of the next sinusoid join into a single two-period step. This wave is power-amplified and the polarity of alternate half sinusoids is reversed in the middle of the low two-period step, by switching in the output stage under control of the second counter. Strict symmetry of the resulting approximation of a sine wave is obtained with few different resistors defining one quarter of the wave shape. The circuit in the frequency divider that produces frequency changes in response to the keying signal is timed by a logic network to switch over only at alternate transitions of the output sinusoidal wave intervals.

REFERENCES:
patent: 3659048 (1972-04-01), Zuerbus
patent: 3668562 (1972-06-01), Fritkin
patent: 3793589 (1974-02-01), Puckette
patent: 3801911 (1974-04-01), Horsten
patent: 3801912 (1974-04-01), Ragsdale
patent: 3991389 (1976-11-01), Dwire

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