Method and circuit for generating spreading codes

Details Method and circuit for generating spreading codes Method and circuit for generating spreading codes

2000-08-08

2004-05-04

Chin, Stephen (Department: 2634)

Pulse or digital communications

Spread spectrum

Direct sequence

C708S253000

Reexamination Certificate

active

06731670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a spreading code generation method and a spreading code generating circuit.
2. Description of the Related Art
Spreading spectrum communication, in particular CDMA (code division multiple access) method implement high-quality speech communications or high-speed data communications. The CDMA is the mainstream of mobile communication methods.
In W-CDMA mobile communication system including a plurality of asynchronously operating base stations, a rapid establishment of the initial synchronizing process is needed. The rapid establishment of the initial synchronization is a key factor for keeping excellent speech qualities or expanding battery services at mobile terminals.
Upon the power-on of the mobile terminals or upon the base station-to-base station handover, synchronism with the base station has to first be established. The establishment of the initial synchronization necessitates spreading codes in a predetermined phase.
A slow spreading code generation speed may impede the rapid initial synchronization establishment.
The spreading codes can typically be M-sequence (maximum-length linearly recurring sequence) spreading codes.
The M-sequence spreading codes are generated by use of a “bit circulative shift register”. The generation of the spreading codes by the bit circulative shift register is effected in accordance with the following procedure.
Data is first fetched from a specific tap of a shift register, which is determined by an M-sequence generator polynomial. The thus fetched data is then added to an output of the shift register. The result of addition is then returned to a first step of the shift register. The above operations are iterated. The M-sequence spreading codes are thus generated with the data cycled.
Such an operation as merely sending data in sequence from the bit circulative shift register will take a substantial time to shift the phase of the spreading code by a desired amount. A technique is thus proposed that uses vector multiplication to implement a rapid phase shift (Japanese Patent Laid-open Pub. No. Hei7-107006).
In the technique disclosed in this publication, the spreading codes serially output from an M-sequence generator (bit circulative shift register) are multiplied by a vector imparting a predetermined shift thereto, with the result that the phase of the spreading codes is shifted by the desired number of steps.
To achieve a high-speed output of the spreading codes by use of the bit circulative shift register, it is necessary to increase shift clock frequencies of the shift register, or alternatively to simultaneously operate a plurality of the bit circulative shift registers.
A limitation may however be imposed on enhancement of the operating speed of the bit circulative shift register. Furthermore, the parallel operation of the bit circulative shift registers will incur the increased circuit scale, resulting in an increase in costs and dissipation currents.
The technique disclosed in Japanese Patent Laid-open Pub. No. Hei7-107006 achieves a rapid phase shift of the spreading codes. The speed per se of successively generating the M-sequence spreading codes depends on the operating speed of the M-sequence generator (bit circulative shift register).
Thus, from a standpoint of successive generation of the spreading codes there still remain problems of a possible limitation arising from the register's performance and of a rise in power consumption and costs.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to remarkably enhance the speed per se of successively generating the sequential spreading codes while suppressing the power consumption and costs.
The present invention makes no use of the bit circulative shift register for generating the spreading codes. Instead, vector operations are effected in sequence to generate the spreading codes in a successive manner.
Data is provided in parallel as output from each of taps of the shift register having a predetermined bit count. Each parallel output data is multiplied by a vector operation coefficient. This imparts to each data a phase shift corresponding to the number of taps of the shift register.
Each phase shifted data is then fed in parallel to the shift register.
These operations are iterated so that the spreading codes are output in parallel and in a successive manner.
In one aspect of a spreading code generation method according to the present invention, n-bit data corresponding to data retained in the bit circulative shift register is provided as parallel output. Each parallel data is then multiplied by a vector operation coefficient so that an n-bit (n-step) phase shift is imparted to each data. These operations are then iterated to provide spreading codes as successive and high-speed output.
In another aspect of the spreading code generation method according to the present invention, upon the completion of generation of a single spreading code sequence, each data stored in the shift register is multiplied by the vector operation coefficient. This allows the phase to shift at a stretch up to the initial state of the spreading code sequence to next be generated. It is thus possible to immediately start the generation of the next spreading code sequence.
In one aspect of a spreading code generating circuit according to the present invention, a closed loop for data cycling is formed by the mutual connections of a register, a vector operating circuit and a selector. With the data cycled, plural-bit spreading codes are provided as parallel output. This achieves a rapid, successive spreading code generation.
In another aspect of the spreading code generating a circuit according to the present invention, a single vector multiplier is shared by a plurality of registers.
The initial synchronism can be established at an earlier stage in the mobile communications by mounting a correlation detecting circuit that incorporates the spreading code generating circuit according to the present invention on mobile communication terminals or mobile communication systems. The provision to the user of pleasant mobile communication environments is thus achieved.


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English Language Abstract of JP 7-107006.

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