Method and circuit for generating dependent clock signals

Details Method and circuit for generating dependent clock signals Method and circuit for generating dependent clock signals

1989-06-02

1991-01-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, H03K 513, H03K 1900

Patent

active

049888927

ABSTRACT:
A method and circuit generate a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal and inverting it to create a second master clock signal that is one hundred eighty degrees out of phase with the first master clock signal. The second master clock signal is used to drive a flip flop type circuit so that the flip flop circuit changes states when the first master clock signal is at a "zero" level and the second master clock signal is at a "one " level. The output of the flip flop circuit is enabled using the first master clock signal. Connected to the output of the tri-state driver is a repeater circuit of the type having an output that remains the same as the input until the input level is changed. The resulting dependent clock signal has a minimal skew with respect to the first master clock signal because the output of the flip flop circuit has become stable by the time the tri-state driver is enabled by the first master clock signal. Thus, the skew line is limited to the delay time of the tri-state driver.

REFERENCES:
patent: 4115706 (1978-09-01), Yamaguchi
patent: 4641048 (1987-02-01), Pollock
patent: 4756006 (1988-07-01), Rickard
patent: 4912340 (1990-03-01), Wilcox et al.
"TTL Clock Generator with Equal Mark/Space", New Electronics, Apr. 6, 1982, vol. 15, No. 7, P. Thompson.
"Clock Generator with Single-Oscillator-Edge Control", IBM Technical Disclosure Bulletin, vol. 30, No. 2, July, 1987.

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