Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-11-26
1999-03-23
Nelms, David
Static information storage and retrieval
Addressing
Sync/clocking
365202, 365194, G11C 700
Patent
active
058869492
ABSTRACT:
A method and a circuit generates a pulse synchronization signal in order to control the reading phase of memory cells in semiconductor integrated, electronic memory devices. The pulse synchronization signal is generated upon sensing a change in logic state on at least one of a plurality of address input terminals of the memory cells to also generate an equalization signal for a sense amplifier. The logic state of said pulse synchronization signal is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal. To this aim, a re-acknowledge circuit portion is provided which is input a corresponding signal to the equalization signal and feedback connected to the output node to drive the discharging of the node with a predetermined delay from the reception of the input signal.
REFERENCES:
patent: 5323359 (1994-06-01), Kayamoto et al.
patent: 5418479 (1995-05-01), Sambandan
patent: 5479374 (1995-12-01), Kobayashi et al.
patent: 5487043 (1996-01-01), Furutani et al.
patent: 5719820 (1998-02-01), Fuji
Bettini Luigi
Defendi Marco
Villa Corrado
Carlson David V.
Mai Son
Nelms David
SGS-Thomson Microelectronics S.R.L.
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