Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-08-20
2004-01-13
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S156000
Reexamination Certificate
active
06677879
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to signal processing, and more particularly to a method and circuit for implementing an analog-to-digital converter (ADC) using folding frequency detector circuits or folding time detector circuits.
BACKGROUND OF THE INVENTION
An analog-to-digital converter (ADC) converts an input analog signal to an output digital signal that is an approximation of the input analog signal. The resolution of an ADC defines the accuracy of the approximation between the output digital signal and the input analog signal. In this regard, the closer the resemblance between the output digital signal and the input analog signal, the greater the resolution of the ADC. ADCs having various architectures are well known in the art. In general, each ADC architecture can have specific characteristics making it suitable or unsuitable for a particular application.
One of the most popular ADC architectures is a pipeline ADC. Pipeline ADCs generally find application in systems operating at speeds of 10-200 MHz and requiring moderate resolution of the order of 10-14 bits. Their power consumption can be classified as being moderate when compared to other types of ADCS. The popularity of pipeline ADCs can be attributed to factors such as their resolution, speed, size and power consumption. A typical architecture of a pipeline ADC can include a plurality of consecutively coupled processing stages that can include a track-and-hold (T/H) circuit, and a summation circuit and amplification circuit coupled to each stage. A major drawback with pipeline ADCs involves latency occurring at various processing stages. For this and other reasons, pipeline ADCs are extremely sensitive to non-linearities affecting offset and gain. ADC based designs typically require complex reference circuitry and precise latch timing in order to ensure output synchronization.
Another popular ADC architecture is the sigma-delta ADC. The sigma-delta ADC typically finds application in systems operating at speeds of about 20 MHz and requiring high resolution of the order of 12-16 bits. A typical sigma-delta ADC can include a comparator and an integrator having a feedback loop containing a 1-bit DAC. In this regard, sigma-delta ADCs can be cheaply produced and can save on expensive printed circuit board (PCB) real estate. Notwithstanding, although sigma-delta ADCs can provide a higher resolution than pipeline ADCs, their application is limited by their speed.
The flash ADC is also a very popular and well known ADC architecture. Although flash ADCs can operate at speeds in excess of 1 GHz, power consumption is extremely high. Furthermore, their cost can be very high when compared to other ADCs.
Although not as fast as flash ADCs, folded ADCs can provide greater design and operating flexibility than flash ADCs. Folded ADCs are well known in the art and operate by folding the analog input voltage to create a repetitive output that varies over a particular input voltage range. Notwithstanding the fact that folded ADCs provide greater design flexibility than flash ADCs, current flash ADCs typically require a quadrupled number of components in order to achieve an increase resolution of two (2) bits.
Given these inflexibilities and other inherent drawbacks of existing ADCs including folded ADCs, there is a need for a method and circuit for providing a more flexible ADC with regard to resolution, power consumption, operating speed and cost.
SUMMARY OF THE INVENTION
The invention provides a method and system for converting an analog input signal to a digital output signal. The method can include the step of converting the analog input signal to at least one intermediate signal having a frequency dependent on the analog input signal. A frequency of the intermediate signal can be divided in order to generate a frequency divided signal. The frequency of the intermediate signal and frequency divided signal can subsequently be determined to provide a determined frequency signal or signals. The determined frequency signal (or signals) of the intermediate signal and the frequency divided signal can be processed in order to generate the digital output signal, which is representative of the analog input signal.
The converting step can further include the step of converting a voltage of the analog input signal to the intermediate frequency dependent signal. The frequency of the intermediate signal can be determined using a first time detector, while the frequency of the frequency divided signal can be determined using a second time detector. Alternatively, the frequency of the intermediate signal can be determined using a first frequency detector, while the frequency of the frequency divided signal can be determined using a second frequency detector.
The processing step can further include the steps of summing component signals of the intermediate signal and summing component signals of the frequency divided signal. The summed components of the intermediate signal and the frequency divided signal can subsequently be combined to generate a combined signal. The combined signal can be the digital output signal that is representative of the analog input signal. Optionally, the processing step can further include weighting the combined signal to generate the digital output signal that can be representative of the analog input signal.
The invention also provides analog-to-digital converter for converting an analog input signal to a digital output signal. The analog-to-digital converter can include means for converting the analog input signal to at least one intermediate signal having a frequency dependent on the analog input signal. Dividing means can be configured to divide a frequency of the intermediate signal to generate a frequency divided signal. Determining means can be configured to determine the frequency of the intermediate signal and the frequency divided signal. Processing means can be configured to process the determined frequency signal of the intermediate signal and the determined frequency signal of the frequency divided signal. The processing means can subsequently generate a digital output signal, which can be representative of the analog input signal.
The converting means of the analog-to-digital converter can further include means for converting a voltage of the analog input signal to the intermediate frequency dependent signal. The determining means can further include means for determining the frequency of the intermediate signal using a first time detector and means for determining the frequency of the frequency divided signal using a second time detector. Alternatively, the determining means can include a first frequency detector and a second frequency detector for determining the frequency of the intermediate signal and the frequency divided signal respectively.
The processing means of the analog-to-digital converter can further include means for summing component signals of the intermediate signal and means for summing component signals of the frequency divided signal. Combining means can be configured to combine the summed components of the intermediate signal and frequency divided signal to generate a combined signal. In this regard the combined signal can be the digital output signal, which is representative of the analog input signal. optionally, the analog-to-digital converter can further include means for weighting the combined signal to generate the digital output signal, which is representative of the analog input signal.
In another aspect of the invention, an analog-to-digital converter for converting an analog input signal to a digital output signal is provided. The analog-to-digital converter can include a voltage-to-frequency converter for converting the analog input signal to an intermediate signal having a frequency dependent on the analog input signal. A frequency divider can be configured to divide a frequency of the intermediate signal to generate a frequency divided signal. A first frequency detector can be configured to determine a frequency of the intermediate signal, whil
Nix Michael A.
Younis Ahmed
Pablo Meles
Wamsley Patrick
Xilinx , Inc.
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