Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-01-12
2003-04-22
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S204000
Reexamination Certificate
active
06553399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for an envelope detection by using a peel cone approximation.
2. Description of the Related Art
An envelope detection circuit is a converting circuit applied to applications such as a spread spectrum communication, an amplitude detection for radar systems, and a receiver demodulation and waveform generation, etc., for finding a square root of the sum of two squares. Primarily, a concept which is different from conventional envelope detection concepts is used in the envelope detection method to achieve effects of both simplifying a circuit configuration and obtaining a low approximation error, which makes approximation to a physical calculated value through a peel cone approximation method.
As shown in
FIG. 1
, the detection circuit disclosed in U.S. Ser. No. 09/049,605, which was filed by the applicant, comprises: an absolute value determining circuit
30
′ for generating absolute values of two inputs X and Y; a maximum/minimum value determining circuit
31
′ for generating a bigger one and a smaller one of absolute values of the inputs X and Y; a delaying circuit
32
′ delaying the output of the maximum/minimum value determining circuit
31
′; a plurality of comparison circuits
41
′~
45
′ and an address decoder
50
′ for generating an address signal of a read only memory
35
′ in which a coefficient table is stored; and a multiplier/adder
34
′, connected to the delaying circuit
32
′ and the read only memory
35
′ to generate a square root of the sum of two squares of inputs X and Y. Because above circuit uses a plurality of comparison circuits
41
′~
45
′ and an address encoder
50
′ to generate an address of the read only memory
35
′, it needs more gate counts and more area; and above circuit has more errors and slower operating speed.
SUMMARY OF THIS INVENTION
The object of the present invention is to eliminate the drawbacks of excessive error and more hardware cost in original application patent. To this end, the present invention provides a method and a circuit to transform two input Rectangular coordination points X and Y to {circumflex over (r)} which is an approximate value of radius r in polar coordinate.
The present invention mainly comprises: an absolute value determining circuit for determining positive values for incoming values of x and y with a 16-bit notation; a maximum/minimum value determining circuit for determining a maximum value and a minimum value for the incoming values of x and y after their positive values are determined; a read only memory for selecting corresponding constant values of a and b stored inside the read only memory in advance based on the address signal; and a multiplier/adder for performing multiplication and addition operations on the constant values of a and b from the read only memory together with the value of x and y from the maximum/minimum value determining circuit and outputting a square root of the sum of two squares of the values of x and y; wherein the characteristic is that there is a divider between the maximum/minimum value determining circuit and the read only memory, used to generate the value of k for the address of the read only memory.
The present structure can also be implemented by software, because of simplicity and less operations of the structure, the implementation by software also has the advantage as above-mentioned.
REFERENCES:
patent: 3829671 (1974-08-01), Gathright et al.
patent: 4553260 (1985-11-01), Belt et al.
patent: 4599701 (1986-07-01), Vojir et al.
patent: 4694417 (1987-09-01), Cantwell
patent: 4736334 (1988-04-01), Mehrgardt
patent: 4747067 (1988-05-01), Jagodnik et al.
patent: 5459683 (1995-10-01), Uesugi et al.
patent: 5862068 (1999-01-01), Onodera
patent: 6070181 (2000-05-01), Yeh
Chiou Chin-Hung
Yeh Yuh-miin
Chung-Shan Institute of Science
Malzahn David H.
William E. Pelton, Esq.
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