Method and circuit for dynamic reading of a memory cell at...

Details Method and circuit for dynamic reading of a memory cell at... Method and circuit for dynamic reading of a memory cell at...

2002-02-13

2003-10-28

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

Reexamination Certificate

active

06639833

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for dynamic reading of a memory cell at a low supply voltage and with low output dynamics.
2. Description of the Related Art
As is known, the need for nonvolatile memories having increasingly larger densities has led to manufacturing multi-level memories wherein the information, stored as charge quantity in a floating-gate region, is encoded by fractioning the entrapped charge. In this way, the characteristic of a multilevel flash cell is described by a number of curves representing the pattern of the drain current Ids as a function of the gate voltage Vgs, each curve being associated to a different logic value. For example
FIG. 1
shows the characteristic of a four-level (2-bit) flash cell which stores the bits “11”, “10”, “01” and “00”, corresponding to threshold voltages Vt
1
, Vt
2
, Vt
3
and Vt
4
.
Reading of multi-level cells is carried out evaluating the current or the voltage.
Current reading is based on comparing the current flowing in a cell at a preset gate voltage Vgs and the current flowing in a reference cell, the characteristic of which is intermediate between the distributions of the programmed cells, as shown in FIG.
2
. The comparison is made after a current-to-voltage conversion, both of the current of the cell and of the reference current.
Current reading has a number of problems, the main ones depend on parasitic resistances, such as source and drain-contact resistance of the cell, resistance of the metal connections, and resistance caused by the pass transistors of the column decoder.
As a whole, the result is a reduction in current dynamics. Consequently, the comparator that compares the voltages after current-to-voltage conversion must have a greater sensitivity. In addition, the actual characteristics differ with respect to the ideal ones, as shown in FIG.
3
. Due to such non-idealities, current reading of multilevel memory cells having more than two bits per cell is difficult, because it is required to distinguish extremely near current levels from one another.
To overcome the above problems, U.S. Pat. No. 5,034,888, in the name STMicroelectronics, Srl, proposes a voltage reading method using a closed-loop circuit (see FIG.
4
). In this circuit, the current of the cell to be read is compared with a reference current, and the gate voltage of the cell is modulated until reaching the equilibrium of the system. Thereby, the gate voltage of the cell reaches a value that can be defined as the threshold value of the cell.
However, also this solution is not free from problems, due to the need for an A/D converter able to read the voltage on the gate terminal of the cell, and to the constraint of not being able to read more than one cell at a time, since the row is in common to more than one cell and cannot assume different voltage values.
The solutions devised for solving the above problems moreover involve other disadvantages (increase in read time, greater area) and in any case call for the capacity to discriminate very small currents. On the other hand, the new technologies, involving a reduction in the cell dimensions, lead in turn to a reduction in the cell current, even though solutions are known for reducing the parasitic effects that determine the losses of linearity.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention improves the reading circuit just described in such a way that it will operate properly even at low supply voltages and will present reduced output dynamics.
An embodiment of the invention is directed to a method for reading a memory cell that includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive integration element. In a first embodiment, the second charge quantities are initially stored in a plurality of capacitive charge-regeneration elements connected alternately and in succession to the capacitive integration element; the second charge quantities are then shared between the capacitive integration element and the capacitive charge-regeneration elements.


REFERENCES:
patent: 6034888 (2000-03-01), Pasotti et al.
patent: 6134147 (2000-10-01), Kaneda
patent: 6459612 (2002-10-01), Satoh et al.

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