Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-11-21
2003-07-29
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S042000, C365S230020, C365S189050, C365S189020, C711S167000
Reexamination Certificate
active
06600693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and circuit for driving a word line and a bit line for a read/write operation of a quad data rate (QDR) SRAM, and in particular to a method and circuit for driving a word line and a bit line for a read/write operation of a QDR SRAM which can perform the read and write operations in one cycle in the QDR device in which the read and write operations are individually performed in a double data rate (DDR), and which can read data in a burst length according to one address variation by using a prefetched method in the read operation.
2. Description of the Background Art
The SRAM performs data input and output through one pin. Since the data input and output are not individually controlled, the SRAM is designed to have limited data input and output frequencies. A zero bus turnaround (ZBT) SRAM has been suggested to solve the foregoing problem, but failed to perform the data input and output at the same time.
In order to solve a problem due to a turnaround time, the QDR SRAM completely separates data input and output pins. That is, the data input and output pins are provided to individually perform the data input and output. Here, the QDR implies that the data input and the data output can be driven in a double data rate (DDR).
However, when the conventional QDR SRAM reads or writes a data in different cycles, it cannot form a frequency in which the input and output are performed in the DDR.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a method and circuit for driving a word line and a bit line for a read/write operation of a quad data rate (QDR) SRAM which can perform the read and write operations in one cycle in the QDR device in which the read and write operations are individually performed in a double data rate (DDR).
Another object of the present invention is to provide a method and circuit for driving a word line and a bit line for a read/write operation of a QDR SRAM which can read data in a burst length according to one address variation by using a prefetched method in the read operation.
In order to achieve the above-described objects of the invention, there is provided a method for driving a QDR synchronous semiconductor memory device including the steps of: enabling a word line for a read operation by being synchronized with a rising edge of one clock cycle, and disabling word line and bit line select signals for the read operation before a falling edge; and enabling a word line for a write operation by being synchronized with the falling edge of the clock cycle, and disabling word line and bit line select signals for the write operation before a rising edge of a succeeding clock cycle.
The step for the read operation includes the steps of: simultaneously reading two memory cells in one read operation among a plurality of memory cells corresponding to the enabled word line; generating a first pulse which becomes a high level by being synchronized with the rising edge of the clock cycle, and which becomes a low level before the falling edge; and outputting data from the two memory cells by respectively synchronizing them with the rising edge and the falling edge of the first pulse. A semiconductor memory device is designed to simultaneously select two cells according to one column select signal in order to read the two cells at the same time.
The step for the write operation includes the steps of: generating a second pulse which becomes a high level by being synchronized with the falling edge of the clock cycle, and which becomes a low level before the rising edge of the succeeding clock cycle; and recording data on two memory cells by respectively synchronizing them with the rising edge and the falling edge of the second pulse.
There is also provided a circuit for driving a QDR synchronous semiconductor memory device, including: an address buffer for buffering an external address signal; a write address storing unit for receiving an address signal corresponding to a write operation from the address buffer, and storing the received signal; a read address storing unit for receiving an address signal corresponding to a read operation from the address buffer, and storing the received signal; and an address combining unit for receiving the write address signal from the write address storing unit and the read address signal from the read address storing unit, and combining the two address signals to be separated in time in one clock cycle.
The address combining unit includes: a read pulse address generating unit for receiving the read address signal from the read address storing unit, and outputting the read address signal synchronized with the rising edge of the clock cycle for a predetermined time of the read operation; a write pulse address generating unit for receiving the write address signal from the write address storing unit, and outputting the write address signal synchronized with the falling edge of the clock cycle for a predetermined time of the write operation; and a multiplexer for combining the output signal from the read pulse address generating unit and the output signal from the write pulse address generating unit.
The read pulse address generating unit finishes outputting the read address signal before the falling edge of the clock cycle. For this, the read pulse address generating unit includes a NAND gate having its one input terminal connected to receive the pulse signal which becomes a high level in the rising edge of the clock cycle and which becomes a low level before the falling edge, and its other input terminal connected to receive the output signal from the read address storing unit. The write pulse address generating unit finishes outputting the write address signal before the rising edge of the succeeding clock cycle. For this, the write pulse address generating unit includes a NAND gate having its one input terminal connected to receive the pulse signal which becomes a high level in the falling edge of the clock cycle and which becomes a low level before the rising edge of the succeeding clock cycle, and its other input terminal connected to receive the output signal from the write address storing unit. The multiplexer includes an OR gate having its one input terminal connected to receive the output signal from the read pulse address generating unit, and its other input terminal connected to receive the output signal from the write pulse address generating unit.
In addition, a method for driving a synchronous semiconductor memory device having a memory cell array for storing data includes the steps of: generating M (M is a natural number) pulses separated in time in one clock cycle when a burst length of the semiconductor memory device is 2N (N is a natural number); combining M addresses in one clock cycle by using the M pulses; and reading or writing 2M data from/on the memory cell array corresponding to the addresses, by respectively synchronizing them with the rising edges and falling edges of the M pulses.
According to the present invention, the read and write operations are performed in one cycle. It is thus possible to perform the read and write operations in the same ratio in the QDR device where the read and write operations are separately performed in the DDR. In addition, the prefetched method is applied to the read operation, so that the QDR SRAM can be designed in a burst length 2 reading and writing two data according to one address variation, a burst length 4 reading and writing four data according to one address variation, and other different burst lengths. Moreover, the word line and bit line decoder can be used through the muxing of the read and write addresses, instead of individually using a write decoder and a read decoder. As a result, a chip layout size is reduced.
REFERENCES:
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5508964 (1996-04-01), Toops
patent: 5559752 (1996-09-01), Stephens, Jr. et al.
patent: 5815459 (1998-09-01), Park et al.
patent: 5898611 (1999-04-01), Y
Hynix / Semiconductor Inc.
Ladas & Parry
Le Vu A.
Nguyen Nam
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