Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1997-11-13
2001-09-11
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S094000
Reexamination Certificate
active
06288697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for driving a display device. More particularly, the present invention relates to a method and a circuit for driving a display device such that the display quality of an active matrix type liquid crystal display device, including active elements such as thin film transistors (TFTs), is less affected by variations of the average of the voltages applied to data lines included in such a display device.
2. Description of the Related Art
First, the fundamental configuration and the operational principles of a conventional digital driver will be described.
FIG. 1A
shows a circuit section corresponding to one output of a conventional three-bit digital driver.
This circuit section corresponds to one of a plurality of data lines included in a liquid crystal display panel.
In the following description, this circuit section will be called a “unit driver circuit”. The conventional three-bit digital driver includes the same number of unit driver circuits as that of the data lines included in the liquid crystal display panel.
As shown in
FIG. 1A
, the unit driver circuit includes: a sampling memory M
SMP
; a holding memory M
H
; and an output circuit section OPC.
The sampling memory M
SMP
samples three-bit digital image data in synchronism with the leading edge of a sampling pulse T
SMP
.
The holding memory M
H
retrieves the image data from the sampling memory M
SMP
and holds the data therein in synchronism with the leading edge of an output pulse LS which is synchronous with a horizontal synchronizing signal.
The output circuit section OPC selectively outputs one of eight different gray-scale voltages V
0
through V
7
to a data line DL
n
depending upon the value of the image data held in the holding memory M
H
. Herein, DL
n
denotes a data line on an n-th column. The gray-scale voltages V
0
through V
7
are supplied from the outside of unit driver circuit to the output circuit section OPC. The output pulse LS is supplied to the holding memory M
H
after the sampling of data has been completed in all of the unit driver circuits included in the digital driver. Herein, the sampling of data refers to a retrieval of the image data into the sampling memory M
SMP
in synchronism with the leading edge of the sampling pulse T
SMP
.
FIG. 1B
shows a specific configuration of the output circuit section OPC shown in FIG.
1
A. The output circuit section OPC includes: a decoder DEC for converting the three-bit image data into eight switch control signals S
0
through S
7
; and analog switches ASW
0
through ASW
7
for receiving the corresponding switch control signals S
0
through S
7
, respectively, and outputting the gray-scale voltages V
0
through V
7
corresponding to the switch control signals S
0
through S
7
, respectively, to the data line DL
n
.
For example, if the value of the image data held in the holding memory M
H
is “4”, only the switch control signal S
4
of the eight switch control signals S
0
through S
7
which are output from the decoder DEC is activated. As a result, only the analog switch ASW
4
of the eight analog switches ASW
0
through ASW
7
is turned ON. In this manner, the gray-scale voltage V
4
input to the analog switch ASW
4
is output to the data line DL
n
.
FIG. 2
shows the waveforms of respective signals in the case of alternating current (AC) driving a liquid crystal display panel. In
FIG. 2
, Hsync denotes a horizontal synchronizing signal, and POL denotes a signal representing either a time period during which the potential of a pixel electrode is charged to be positive with respect to a voltage V
COM
applied by a common electrode (hereinafter, such a time period will be referred to as a “positive drive time period”) or a time period during which the potential of the pixel electrode is charged to be negative with respect to the voltage V
COM
applied by the common electrode (hereinafter, such a time period will be referred to as a “negative drive time period”). The signal POL will be called a “polarity signal”.
V
0
, V
2
, V
5
and V
7
respectively denote the potentials of the gray-scale voltages V
0
, V
2
, V
5
and V
7
during the positive drive time period, while −V
0
, −V
2
, −V
5
and −V
7
respectively denote the potentials of the gray-scale voltages V
0
, V
2
, V
5
and V
7
during the negative drive time period. It is noted that, in
FIG. 2
, the gray-scale voltage V
0
having a maximum potential difference with respect to the common electrode voltage V
COM
(and corresponding to the gray-scale data “0”), the gray-scale voltage V
7
having a minimum potential difference with respect to the common electrode voltage V
COM
(and corresponding to the gray-scale data “7”) and the gray-scale voltages V
2
and V
5
having potentials intermediate between the potentials of V
0
and V
7
(and corresponding to the gray-scale data “2” and “5”, respectively) are selectively shown from the eight gray-scale voltages V
0
through V
7
, and the other gray-scale voltages V
1
, V
3
, V
4
and V
6
are omitted.
LS denotes a latch strobe signal which is an output pulse synchronous with the horizontal synchronizing signal Hsync. In response to the signal LS, the image data in the sampling memory M
SMP
is retrieved into the holding memory M
H
, and is simultaneously output to the output circuit section OPC.
Moreover, the AC drive shown in
FIG. 2
is performed in accordance with a row inversion drive method (also called a “line inversion drive method”) in which the positive and the negative drive time periods alternate on the basis of one row (i.e., one gate line) of a liquid crystal display panel. In this case, considering each row, the waveform of each gray-scale voltage is determined such that the positive and negative polarities of each gray-scale voltage are inverted on a frame (i.e., a vertical interval) basis. That is to say, the waveform of each gray-scale voltage is inverted in synchronism with both the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync.
FIG. 3
shows the waveform of the gray-scale voltage V
0
over two frames. The vertical synchronizing signal Vsync is used for defining one frame (vertical interval) and the horizontal synchronizing signal Hsync is used for defining one horizontal interval. As can be understood from
FIG. 3
, the polarity of the gray-scale voltage V
0
is inverted every horizontal interval within one frame, and the polarity of the gray-scale voltage V
0
during a horizontal interval in the former frame is inverse of the polarity of the gray-scale voltage V
0
during the corresponding horizontal interval in the latter frame.
In accordance with a conventional drive method, as shown in
FIG. 2
, the leading edge of the output pulse LS is synchronous with the time at which the level of the gray-scale voltage is changed. This is a condition necessarily determined by the fact that output of new data is started in response to the output pulse LS. As a result, the ratio of the length of a time period during which a desired voltage is output from the driver to the data line to the entire length of a positive
egative drive time period can be maximized.
FIG. 4
shows the waveform of a voltage W
0
to be output from a unit driver circuit to a data line over two frames (vertical intervals) in the case of writing display data “0” onto a pixel and the waveform of a voltage W
07
to be output from the unit driver circuit to the data line over two frames (vertical intervals) in the case of alternately writing the display data “0” and display data “7” onto the pixel, together with the waveforms of the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync.
In
FIG. 4
, Va denotes an average voltage of the output voltage W
0
in one frame period. As shown in
FIG. 4
, in the case of writing the display data “0” onto the pixel, the average voltage Va is constant in two adjacent frames.
In
FIG. 4
, Va
1
denotes an average voltage of the output voltag
Eto Sunao
Okada Hisao
Frenel Vanel
Nixon and Vanderhye
Shalwala Bipin
Sharp Kabushiki Kaisha
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