Method and circuit for determining frequency and time...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase

Reexamination Certificate

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Details

C327S003000, C327S043000

Reexamination Certificate

active

06621307

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to signal processing, and more particularly to a method and system for determining frequency and time variations between electronic signals.
BACKGROUND OF THE INVENTION
In signal processing applications, it is often necessary to determine certain parameters of a signal in order to accurately track the signal. These applications can include, but are not limited to, frequency control, symbol synchronization, bit synchronization and coherent carrier tracking. Phase-locked loops (PLLs) are well known in the art and they can function as a signal tracking tool. A PLL is an electronic circuit that can be configured to control an oscillator so that the oscillator produces a signal having a constant phase angle relative to a reference signal. A PLL can be configured to control a voltage controlled oscillator (VCO). In this regard, a variable tuning voltage can be applied to an input of the VCO to produce an output that varies over a wide frequency range. Notably, by applying a specified tuning voltage, the VCO can produce one or more signals having a particular frequency.
The resolution of a circuit can be used to define the variation between an input signal and a reference signal. In general, the smaller the variation between the input signal and the reference signal, the greater the accuracy or resolution. In contrast, the greater the variation between the input signal and a reference, the lesser the accuracy or resolution. Notably, less resolution will require less timing samples or counts to achieve synchronization. For example, a system that requires a 5% resolution or accuracy may require 128 counts to achieve such precision. However, a system that requires 0.03% accuracy may require 16,384 counts. In this context, a 5% accuracy provides less precision than a 0.03% accuracy or resolution. Importantly, the greater the required resolution, the greater the number of required counts and the greater the processing time. This greater processing time can adversely affect system speed and performance.
In certain applications, it can be critical to maintain a minimal resolution in order to maintain functionality of a circuit or particular integrated circuit (IC). For example, it can be necessary to switch a PLL from a first reference clock signal to a second reference clock signal. Under normal operation, the PLL will attempt to converge to the frequency of the first reference signal and once the desired accuracy is met, switching to the second reference signal can occur. However, if the frequency of the PLL and the second reference clock signal are not within a certain minimal resolution at the switchover point, signal divergence can result in a loss of synchronization, which can ultimately cause a loss of system functionality. To prevent divergence, greater resolution can be required.
Given these inflexibilities and other inherent drawbacks, there is a need for providing a method and circuit for determining variations between electronic signals in order to overcome the limitations described.
SUMMARY OF THE INVENTION
The invention provides a method for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal. The method can include the step of generating a plurality of time shifted input clock signals that are time shifted relative to the input clock signal. The plurality of time shifted signals can be sampled at periodic intervals relative to the reference clock signal. Sampled values for the time shifted signals can be compared with values for the reference clock to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal. The variation can include a condition wherein the frequency of the input clock signal can be less than the frequency of the reference clock signal, or the frequency of the input clock signal can be greater than the frequency of the reference clock signal, and the frequency of the input clock signal can be equal to the frequency of the reference clock signal.
The generating step can further include the step of shifting each of the plurality of time shifted signals by an amount equivalent to the period of the input clock signal divided by the number of input clock signals. The number of input clock signals includes the input clock signal and the time shifted versions of the input clock signal. The time shifted versions of the input clock signal can all have the same frequency.
The sampling step can further include the step of sampling at least one of the plurality of time shifted signals on a first rising edge of the reference clock signal to yield a first sampled value for at least one of the plurality of time shifted signals. A value for one or more of the time shifted signals can subsequently be stored in a flip-flop or register. The value for the one or more of the plurality of time shifted signals can be stored on a first falling edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal. Furthermore, one or more of the plurality of time shifted signals can be sampled on a second rising edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal to yield a second sampled value for one or more of the plurality of time shifted signals. Finally, the first and second sampled value for one or more of the plurality of time shifted signals can be compared to determine how the frequency of the input clock signal is varied from the frequency of the reference clock signal.
In another aspect of the invention, an electronic circuit can be provided for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal. The electronic circuit can include means for generating a plurality of time shifted input clock signals. The time shifted signals can be configured so that they can be shifted relative to the input clock signal. Means can be provided for sampling the plurality of time shifted signals at periodic intervals relative to the reference clock signal. Comparing means can be configured for comparing values for the sampled time shifted signals with values for the reference clock signal to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal. The variation can include a condition where the frequency of the input clock signal can be less than the frequency of the reference clock signal, the frequency of the input clock signal can be greater than the frequency of the reference clock signal, or the frequency of the input clock signal can be equal to the frequency of the reference clock signal.
The generating means of the electronic circuit can further include means for shifting each of the plurality of time shifted signals by an amount equivalent to the period of the input clock signal divided by the number of input clock signals. The number of input clock signals can include the input clock signal and the shifted versions of the input clock signals. The time shifted signals can be configured so that they can all have the same frequency.
The sampling means can further include means for sampling at least one of the plurality of time shifted signals on a first rising edge of the reference clock signal to yield a first sampled value for one or more of the plurality of time shifted signals. A flip-flop or register can be configured to store a value for one or more of the plurality of time shifted signals. The storing means can store the first sampled value of one or more of the plurality of time shifted signals on a first falling edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal. One or more of the plurality of time shifted signals can be sampled on a second rising edge of the reference clock signal occurring subsequent to the first rising edge of the reference clock signal, to yield a second sampled value for one or more of the p

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