Method and circuit for detecting errors in digital signals

Details Method and circuit for detecting errors in digital signals Method and circuit for detecting errors in digital signals

1979-05-21

1981-04-28

Atkinson, Charles E.

Excavating

371 56, 375 19, G06F 1100

Patent

active

042649722

ABSTRACT:
A digital signal constituted by a stream of bits is so encoded that its running digital sum (RDS) is confined to a range defined by predetermined lower and upper permissible limits, i.e., absent transmission error. Instead of using a forwards-backwards digital counter to monitor the RDS, with its associated expense and relatively high power consumption when high transmission rates are involved, use is made of an analog integrator which integrates the digital signal to be monitored and generates an analog RDS signal. A digit-error signal is generated when the analog RDS signal attempts to exceed a predetermined analog value corresponding to the upper permissible limit of the RDS or to fall below a predetermined analog value corresponding to the lower permissible limit of the RDS. When the analog RDS signal makes such an attempt it is positively limited to an analog value corresponding to the affected one of the lower and upper permissible values of the RDS and for so long as such attempt continues, this constituting an advantageous way of terminating the response of the error-detecting system to the detected digit error.

REFERENCES:
patent: 3439330 (1969-04-01), Sipress et al.
patent: 3573729 (1971-04-01), Gunn et al.
patent: 3757296 (1973-09-01), Gibson
patent: 3902117 (1975-08-01), Sheppard
patent: 4070646 (1978-01-01), Sandlin
patent: 4110691 (1978-08-01), Lender

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