Method and circuit for configuring memory core integrated...

Details Method and circuit for configuring memory core integrated... Method and circuit for configuring memory core integrated...

2011-08-02

2011-08-02

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S052000

Reexamination Certificate

active

07990746

ABSTRACT:
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

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