Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Generating sawtooth or triangular output
Reexamination Certificate
2000-02-02
2002-01-15
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Generating sawtooth or triangular output
C327S138000, C327S140000, C327S341000
Reexamination Certificate
active
06339349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods and circuitry for generating ramped voltage signals having controlled maximum amplitude, without use of a comparator. In preferred embodiments, the invention is a switching controller which generates at least one ramped voltage signal (for use in generating at least one pulse width modulated power switch control signal for a DC-to-DC converter) such that each ramped voltage signal has a controlled maximum amplitude.
2. Description of the Related Art
In power supply circuitry, it is often desired to produce a ramped voltage or multiple, parallel channels of ramped voltages. For example, in some DC-to-DC converters (sometimes referred to as interleaved PWM DC-to-DC converters, where “PWM ” denotes “pulse width modulated”), multiple channels of ramped voltages are provided to comparator circuitry for use in generating power switch control signals for controlling the duty cycle of each power switch of the DC-DC converter and thus the amplitude of the DC output voltage. The waveforms and maximum amplitudes of the ramped voltages are identical (to the extent practical) except that each has a different phase than the others.
More generally, circuitry providing ramped voltage signals with controlled maximum amplitude is useful for a wide variety of applications, including but not limited to interleaved PWM DC-to-DC converter applications. However, when implementing such circuitry (especially when implementing it as an integrated circuit or part of an integrated circuit), process and temperature variations typically cause variations in the characteristics (e.g., maximum amplitude) of the ramped voltages.
FIG. 1
is a conventional DC-to-DC converter which includes current mode switching controller
1
implemented as an integrated circuit, and boost converter circuitry which is external to controller chip
1
. The boost converter circuitry comprises NMOS transistor N
1
(which functions as a power switch), inductor L, current sense resistor R
s
, Schottky diode D, capacitor C
out
, feedback resistor divider R
F1
, and R
F2
, compensation resistor R
c
, and compensation capacitor C
c
, connected as shown. The
FIG. 1
circuit produces a regulated DC output voltage V
out
across load R
o
, in response to input DC voltage V
in
.
Controller chip
1
includes oscillator
2
(having a first output and a second output), comparator
8
, driver
6
which produces an output potential V
DR
at pad
12
(to which the gate of switch N
1
is coupled), latch
4
(having “set ” terminal coupled to oscillator
2
, “reset ” terminal coupled to the output of comparator
8
, and an output coupled to the input of driver
6
), error amplifier
7
(having a non-inverting input maintained at reference potential V
ref
), and circuit
9
(having a first input coupled to the second output of oscillator
2
, a second input coupled to pad
13
, and an output coupled to the inverting input of comparator
8
).
Pad
13
is at potential V
c
, which is determined by the output of error amplifier
7
(in turn determined by the difference between the instantaneous potential at Node A and the reference potential V
ref
) and the values of external resistor R
c
and capacitor C
c
. Reference potential V
ref
is set (in a well known manner) by circuitry within chip
1
, and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V
out
, resistors R
F1
, and R
F2
with the appropriate resistance ratio R
F1
/R
F2
are employed.
Oscillator
2
asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positivegoing leading edge of this pulse train sets latch
4
. Each time latch
4
is set, the potential V
DR
asserted by driver
6
to the gate of transistor N
1
causes transistor N
1
to turn on, which in turn causes current I
L
from the source of N
1
to increase in ramped fashion (more specifically, the current I
L
increases as a ramp when transistor N
1
is on, and is zero when transistor N
1
is off. The current through diode D is zero when N
1
is on, it increases sharply when N
1
switches from on to off, then falls as a ramp while N
1
is off, and then decreases sharply to zero when N
1
switches from off to on). Although transistor N
1
turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential R
ref
and the instantaneous potential at Node A) that have arbitrary phase relative to the pulses of the periodic clock pulse train.
Oscillator
2
asserts ramped voltage V
R
(which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at its second output. Circuit
9
asserts the potential V
c
−V
R
to the inverting input of comparator
8
. Assertion of the potential V
c
−V
R
(rather than V
c
) to comparator
8
is necessary for stability.
The non-inverting input of comparator
8
is at potential V
s
=I
L
R
s
, which increases in ramped fashion in response to each “set ” of latch
4
by oscillator
2
. When V
s
=V
c
−V
R
(after latch
4
has been set), the output of comparator
8
resets latch
4
, which in turn causes the potential V
DR
asserted by driver
6
to the gate of transistor N
1
to turn off transistor N
1
. Thus, by the described use of both of the signals output from oscillator
2
and feedback asserted to error amplifier
7
from Node A, controller chip
1
switches transistor N
1
on and off with timing that regulates the output potential V
out
of the
FIG. 1
circuit.
FIG. 2
is a diagram of a conventional circuit for generating a ramped voltage V
R
of the type mentioned with reference to FIG.
1
. In the
FIG. 2
circuit, which is typically implemented as part of a controller chip, the voltage across capacitor C
T
is the ramped voltage V
R
. The voltage across capacitor C
T
increases while switch Q
1
(implemented as a transistor) is open (i.e., when no current flows through the channel of Q
1
), as current flows from the top rail through resistor R
T
to the top plate of the capacitor, and decreases rapidly when switch Q
1
is closed to cause capacitor C
T
to discharge. Comparator
16
compares the output potential V
R
with a first reference potential Ref
1
, and asserts a “reset ” signal to latch
15
when the output potential rises to the first reference potential Ref
1
. In response to the reset signal, latch
15
asserts a control signal which causes switch Q
1
to enter its closed state. A second comparator
17
compares the output potential V
R
with a second reference potential Ref
2
(which is lower than reference potential Ref
1
), and asserts a “set ” signal to latch
15
when the output potential falls to the second reference potential Ref
2
. In response to the set signal, latch
15
asserts a control signal which causes switch Q
1
to enter its open state.
However, the conventional circuit of
FIG. 2
has a number of disadvantages and limitations, including the following:
large (in terms of area on the controller chip) and complex circuitry is required to implement each of its comparators (comparators
16
and
17
). Even larger and more complex circuitry is required to implement a larger number of comparators in DC-to-DC converters having multiple power channels, in which each of multiple channels has a set of one or more comparators for use in generating a ramped voltage;
to generate ramped voltage V
R
with a very high frequency (very short period), it may be necessary to implement each comparator to have low propagation delay (e.g., in the range from 10 nsec to 15 nsec), which necessitates high performance, high quiescent current comparator designs; and
due to use of the comparators (comparators
16
and
17
), the ramped voltage V
R
has a frequency dependent offset. It is difficult to compensate for the nonlinear variation (with frequency) of the characteristics of ramped voltage V
R
, and it may be impractical to implemen
Callahan Timothy P.
Girard & Equitz LLP
Luu An T.
National Semiconductor Corporation
LandOfFree
Method and circuit for comparator-less generation of ramped... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and circuit for comparator-less generation of ramped..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for comparator-less generation of ramped... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2820579