Method and circuit for checking operation of input buffers of a

Details Method and circuit for checking operation of input buffers of a Method and circuit for checking operation of input buffers of a

1995-05-31

1997-11-11

Baker, Stephen M.

Excavating

371 223, G01R 313173, G01R 313185

Patent

active

056871805

ABSTRACT:
Output signals of input buffers connected to the external input terminals of the semiconductor circuit are stored in respective memories. The memories are connected in series. Data of the memories are serially output from an external output terminal of the semiconductor circuit. In the above-mentioned operations, a pulse for storing the output signals of the input buffers into the memories, for selecting one of an output signal of the internal circuit and the data stored in the memories, and outputting the selected one from the external output terminal, is supplied via another external input terminal for a test. A pulse for connecting the memories in series is also supplied via a further external input terminal. The output signals of the input buffers can be output from the semiconductor circuit, without any operation of the internal circuit.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3790885 (1974-02-01), James
patent: 4074150 (1978-02-01), Buckley, III et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4488259 (1984-12-01), Mercy
patent: 4503386 (1985-03-01), Das Gupta et al.
patent: 4566104 (1986-01-01), Bradshaw et al.
Williams et al., Proceedings Of The IEEE, vol. 71, No.1 (Jan. 1983), pp. 98-112, "Design for Testability-A Survey".
Patent Abstracts Of Japan, vol. 8, No. 48 (Mar. 3, 1984) p. 258.
Gschwind, H. et al., Design of Digital Computers, Springer-Verlag, 1975, pp. 68-70.
Komonytsky, D., "Synthesis of Techniques Creates Complete System Self-Test", Electronics, Mar. 10, 1983, pp. 110-115.
IBM Technical Disclosure Bulletin, Goel et al., "Functionally Independent AC Test for Multi-Chip Packages", vol. 25, No. 5, Oct. 1982, pp. 2308-2310.
Classnotes for LSI Logic's CMOS Gate Array Training Class for the LDS III, p. 63, Testing, Jul. 1985.

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