Method and circuit for calibration of flash analog to digital co

Coded data generation or conversion – Converter compensation

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341120, H03M 106

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active

059908149

ABSTRACT:
A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.

REFERENCES:
patent: 4097860 (1978-06-01), Araseki et al.
patent: 4251803 (1981-02-01), Debord et al.
patent: 4380005 (1983-04-01), Debord et al.
patent: 4408349 (1983-10-01), Yukawa
patent: 4547763 (1985-10-01), Flamm
patent: 4799041 (1989-01-01), Layton
patent: 4803382 (1989-02-01), Tanimoto et al.
patent: 4864437 (1989-09-01), Couse et al.
patent: 4979055 (1990-12-01), Squires et al.
patent: 5170299 (1992-12-01), Moon
patent: 5255136 (1993-10-01), Machado et al.
patent: 5297184 (1994-03-01), Behrens et al.
patent: 5321559 (1994-06-01), Nguyen et al.
patent: 5335365 (1994-08-01), Ballantyne et al.
patent: 5345342 (1994-09-01), Abbott et al.
patent: 5384671 (1995-01-01), Fisher
patent: 5397936 (1995-03-01), Wang
patent: 5422760 (1995-06-01), Abbott et al.
patent: 5424881 (1995-06-01), Behrens et al.
patent: 5459679 (1995-10-01), Ziperovich
patent: 5572558 (1996-11-01), Beherns
patent: 5576904 (1996-11-01), Behrens
patent: 5638230 (1997-06-01), Kadlec
patent: 5642243 (1997-06-01), Bliss
McCall, K. J. et al., "A 6-bit 125 MH CMOS A/D Converter", Proceedings of the Custom Integrated Circuits Conference, Boston, May 3-6, 1992, No. Conf. 14; pp. 16.8.1-16.8.4, XP000340926, IEEE.
Glincman, M., "CMOS/SOS Flash ADC Speeds on Low Power for Low Cost", Electronic Design, vol. 28, No. 24, Nov. 1980, pp. 227-231, XP002086479, Hasbrook Heights, NJ.
International Search Report, Jan. 22, 1999.
International Search Report, Dec. 18, 1998.
Cideciyan et al., "A PRML System for Digital Magnetic Recording," IEEE J. on Sel. Com.., 10, Jan. 1992.
Coker et al., "Implementation of PRML in a Rigid Disk Drive," IBM Storage Systems Products Division, Manuscript received Jul. 7, 1991.
fields et al., "SA 19.1: A 200Mb/s CMOS EPRML Channel with Integrated Servo Demodulator for Magnetic Hard Disks," IEEE Int'l Solid-State Circuits Conf, Feb. 8, 1997.
Goodenough, "DSP Technique Nearly Doubles Disk Capacity," Electronic Design, 53-57,Feb. 4, 1993.
Reed et al., "Performance of A d=0 Demod/Remod Detector With Partial Erasure Matching," Cirrus Logic, Manuscript received Feb. 4, 1997.
Spalding et al., "SA 19.5: A 200Msample/s 6b Flash ADC in 0.6 .mu.m CMOS," IEEE International Solid-State Circuits Conference, Feb. 10, 1996.
Spurbeck et al., "Interpolated Timing Recovery for Hard Disk Drive Read Channels," IEEE, Aug., 1997.
Tuttle et al., "TP 4.2: A 130Mb/s PRML Read/Write Channel with Digital-Servo Detection," IEEE International Solid-State Circuits Conference, Feb. 8, 1996.
Vanderkooy et al., "Resolution Below the Least Significant Bit in Digital Systems with Dither," J. Audio Eng. Soc., 32(3), Mar. 1984.
Welland et al., "FA 17.1: A Digital Read/Write Channel with EEPR4 Detection," IEEE International Solid-State Circuits Conference, Feb. 18, 1994.
Welland et al., "Implementation of a Digital Read/Write Channel with EEPR4 Detection," IEEE Transactions, Magnetics; 31(2), Mar. 1995.
Welland et al., "Implementation of a Digital Read/Write Channel with EEPR4 Detection,"--Outline; Crystal Semiconductor Corporation and Cirrus Logic; TMRC '94 Session:F2.
Yamasaki et al., SA 19.2: A 1,7 Code EEPR4 Read Channel IC with an Analog Noise Whitened Detector, IEEE International Solid-State Circuits Conference, Feb. 8, 1997.

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