Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
2001-08-30
2003-06-10
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S129000, C330S140000
Reexamination Certificate
active
06577196
ABSTRACT:
The invention relates to a method and circuit for automatic gain control of a signal amplifier, which is customarily used in integrated circuits for service-integrated communications networks ISDN, broadband data communication and networks.
BACKGROUND
In communications technology, both user data and the clock signal on which the user data is based are conventionally transmitted over the transmission channel. At the receiver end, both the user data and the clock signal are then recovered from the received data mixture by means of a CDR (Clock and Data Recovery) circuit. The amplitude of the received data signal has an amplitude attenuation which is dependent on the length of the transmission path. Because the length of the transmission path, and thus the amplitude attenuation, are generally not known, it varies the signal amplitude of the received signal correspondingly. In addition, in many applications the amplitude of the transmission signal which is input into the transmission path is not known. In order to ensure the method of operation of the CRD circuit, an adjustable amplifier attenuator (VGA; Variable Gain Amplifier) is therefore connected between the output of the transmission path or of the transmission channel and the input of the CDR circuit. The adjustable signal amplifier is conventionally operated in a control loop (AGC: Automatic Gain Control Loop) in such a way that a signal with a constant amplitude value is output to the CDR circuit connected downstream of the signal amplifier VGA by the adjustable amplifier VGA independently of the value of the received signal amplitude of the input signal.
The voltage or signal amplitude of the signal output by the variable signal amplifier is conventionally set in such a way that it corresponds to a predefined reference voltage or reference signal amplitude. The output signal of the adjustable signal amplifier is compared here with the reference voltage in a comparator. The signal which is output by the comparator signal sets the gain of the controllable signal amplifier over a controlled system in such a way that the output signal voltage of the adjustable signal amplifier corresponds to the reference voltage. The conventional analogue gain control is defined by a relatively high level of precision of the control, but has the disadvantage that the analogue circuit arrangement is more difficult to integrate in comparison with digital circuit arrangements and requires additional circuit components.
A purely digital implementation of the gain control circuit is relatively easy to integrate on a chip and affords the possibility of rapid conversion to new manufacturing technologies by the use of synthesis tools. The digital implementation is additionally insensitive to process fluctuations in the manufacturing process of the integrated circuit. A disadvantage of a purely digital gain control circuit is however the inherent quantization by the digital discrete representation of numerical values within the control loop. In a purely digital circuit arrangement and implementation of the gain circuit, control precision can therefore be achieved only to the smallest discretization level.
SUMMARY
The object of the present invention is therefore to provide a gain control circuit and a method for automatic gain control of the signal amplifier in which the gain control is carried out with a very high degree of precision and can be simultaneously easily
The invention provides an automatic gain control circuit for setting the signal gain of a signal amplifier having
a peak value detector for measuring the signal amplitudes of the analogue signal which is amplified by the signal amplifier;
a comparator circuit which compares the measured signal amplitudes with an upper amplitude threshold value and et lower amplitude threshold value and generates digital range display data items which indicate whether the measured signal amplitudes lie below the lower amplitude threshold value, between the two amplitude threshold values, or above the upper amplitude threshold value, and having
a digital control circuit which incrementally changes the gain of the signal amplifier as a function of the generated digital display data until the digital range display data indicate that the measured signal amplitudes between the two amplitude threshold values lie in a lock-in amplitude range.
The threshold values of the comparator circuit can preferably be set in an analogue fashion.
In one preferred embodiment, the peak value detector carries out a measurement sequence in order to measure a series of signal amplitudes which are each compared with the amplitude threshold values by the comparator circuit in order to generate a range display data group composed of a plurality of range display data items.
The digital control circuit changes the signal gain of the signal amplifier incrementally until the portion of the digital range display data items of a range display data group which indicate that the measured signal amplitudes lie in the lock-in amplitude range exceeds a predefined first minimum portion threshold value.
This provides the particular advantage that noise and interference (spikes) within the analogue signal amplifiers which usually occur in the voltage supply and in the signal path are very largely suppressed.
In a further particularly preferred embodiment, after the lock-in amplitude range has been reached, the digital control circuit keeps the gain of the signal amplifier constant until the portion of the digital range display data items of a range display data group which indicate that the measured signal amplitudes lie in the lock-in amplitude range drops below a predefined second minimum portion threshold value.
This digital hysteresis improves the adaptation reliability and the signal noise tolerance of the automatic gain control.
The minimum portion threshold values are preferably adjustable.
The second minimum portion threshold value is preferably smaller than the first minimum portion threshold value here.
In a particularly preferred embodiment, the gain level increment of the gain levels with which the signal gain of the signal amplifier can be incrementally changed is also adjustable.
The automatic gain control circuit preferably has a memory for storing the gain level increment and the two minimum portion threshold values.
The digital control circuit preferably has a display data buffer for buffering the generated digital range display data.
The invention also provides a method for automatic gain control of a signal amplifier having the following steps, namely
measuring a sequence of signal amplitudes of a received analogue signal,
comparing the measured signal amplitudes with a lower analogue adjustable amplitude threshold value and an upper analogue adjustable amplitude threshold value,
generating a range display data group composed of a sequence of range display data items, a range display data item indicating in each case for an associated measured signal amplitude whether the measured signal amplitude lies below the lower amplitude threshold value, between the two amplitude threshold values or above the upper amplitude threshold value,
incremental changing of the signal gain of the signal amplifier until the portion of the range display data items of a range display data sequence which indicates that the associated measured signal amplitudes between the two amplitude threshold values lie in a lock-in amplitude range exceeds a predefined minimum portion threshold value.
Preferred embodiments of the automatic gain control circuit according to the invention and of the method according to the invention for automatic gain control of the amplifier will be described below with reference to the appended drawings in order to explain features essential to the invention.
In the drawing:
REFERENCES:
patent: 4124825 (1978-11-01), Webb et al.
patent: 4360787 (1982-11-01), Galpin
patent: 5051707 (1991-09-01), Fujita
patent: 6038432 (2000-03-01), Onoda
patent: OS 2 161 657 (1973-06-01), None
Choe Henry
Fish & Richardson PC
Infineon - Technologies AG
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